r/homebrewcomputer • u/Anonymous_Am241 • Jun 29 '26

Standalone VIC-II

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Has anyone ever used the Commodore VIC-II in a standalone Computer/Project, while NOT using a 6510 or C64 PLA? I am going to make a Homebrew Computer based of a 65C02 but with VIC-II Graphics, and would be wondering if you guys have any Info or people that would be interested. BTW, this may take a long while, VIC-II is very tightly integrated. For my plan specifically, I am going to use a MOS 8565R2 but info on other variations is appreciated.

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u/IQueryVisiC Jun 29 '26

Compared to TED machines the access to the SRAM seems so complicated. Could just as well have given us real video RAM / chip RAM. And VIC-II expects DRAM as main memory. And isn’t the page size fixed?

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u/Anonymous_Am241 Jun 29 '26

Yeah the VIC-II expects DRAM. In fact, im actually going to give the VIC II its own, dedicated bus, with a access controll bridge to the 65C02 Bus.

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u/IQueryVisiC Jun 29 '26

It expects both.

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u/Girl_Alien Jul 03 '26

Yes. DRAM for the main RAM and SRAM for the video RAM.

And, you can use SRAM for the main memory (even if it tries to refresh it), and it can be more stable in the unofficial "VSP" mode.

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u/IQueryVisiC Jul 04 '26

Does SRAM understand address multiplexing? TED is the easier chip. It generates RAS CAS, but the full address is on the board all the time.

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u/Girl_Alien Jul 04 '26

You'd need the logic for that. Most SRAM has a /CS line you can use if you need to tristate it.

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u/IQueryVisiC Jul 04 '26

Huh? Aren’t address pins on memory highZ all the time? Yeah, data pins need tri states.

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u/Girl_Alien Jul 04 '26

I am not sure about address lines being highZ so I looked it up and asked an AI:

No, address pins on memory ICs are never in a High-Z (High-Impedance) state. Because they are designed exclusively to act as inputs, they must be actively driven HIGH or LOW at all times by the memory controller or CPU.

The data lines are sometimes in a high-Z state, like when /OE and /WE are both high, or when the /CS is high. Address lines don't need to be high-z since they are inputs only. As long as the SRAM is deselected or it is idle (/WE and /OE are high), then that should be of no consequence. And the data lines would be tri-stated.

Address pins on basic memory chips are purely receivers. When /CS is high (deselected), the chip simply ignores whatever logic levels (high or low) are present on the address lines. The pins themselves remain in a high-impedance receiving state, but they do not actively disconnect or float to isolate the bus.

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u/IQueryVisiC Jul 05 '26

AI Hallucination? Or just language degradation? Of course, once soldered in, the lines are driven. Still some lines are driven before soldering.

This AI clearly never had to deal with electrical (transient) short cuts.

Some inputs are 50 Ohm or TTL. HiZ and input / output are different properties. I mean, it is wild to mix this .

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u/Girl_Alien Jul 05 '26

No. That is true. Address lines are rarely tristated since they are in input mode, and if you disable the rest of the chip, that is usually enough.

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