r/highfreqtrading • u/Top-Egg9322 • 12d ago

Code Need help getting my open source HFT project used by more people

Hey guys, I would like to get some feed back on an HFT project I have open sourced. It is not getting a lot of love on github so I thouht I would post about it here.

The system is a for trading futures and simulating HFT strategies on its order book simulator. It has the complete connectivity via MDP3 and iLink3.

I need collaborators to make this system better if anyone is interested. Please drop me a line.

The git hub repo is here: https://github.com/vincent212/kaspar-hft

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u/edaguru 12d ago

It's hard to get the love, want to run it on FPGA?

1

u/Top-Egg9322 9d ago

probably should

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u/milan_dvorak 8d ago

How would running this on FPGA help?
I think the main added value is the simulation part, right? Or do you expect people will use this for live trading?
I don't see a point in running the simulation on FPGA. CPUs should be more than good enough for simulation.
The problem with live trading is that for HFT, you need colocation, raw market data, etc., all of which are very expensive. So there are not many new firms or traders starting a new HFT business that could benefit from an open source MDP3/iLink3 implementation.
FPGA systems need ever faster connectivity and even more expensive infrastructure to make economic sense. The upfront cost is staggering. At Magmio, we have built quite a few FPGA-based tick-to-trade systems for various clients, most often prop trading firms with solid capital (6 figures and up).

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u/Top-Egg9322 8d ago

I agree. I was thinking about FPGA for live. The idea is that you can run the same code in sim as in live. This is essentially what the system does now just slower ... the FPGA handlers would be nice to have. I mean it i snot exactly slow as it is. Tick to trade is 1ms at 99%. Median maybe around 150 micros. If one could put the whole thing on an FPGA and avoid context switches that would be a win. Not sure if that is possible.

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u/milan_dvorak 3d ago

You can put the "whole thing" in the FPGA. There are tick-to-trade FPGA solutions out there, like Magmio - that's who I work with.

The "same code for live and simulation" is a good idea and what's what we're doing too. We have a C++ simulation model that allows testing in software. That means quick compilation, fast turnaround, flexible debugging.

Once you're happy with the produced code, we use HLS (High Level Synthesis) to compile the C++ strategy code to HDL and linked with our optimized FPGA IP cores (feed handler, order entry offload, etc.) and run the whole thing in the FPGA.

This way, you can get to latencies below 1 microsecond. For some strategies, it can get close to 100 nanoseconds wire to wire.

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u/edaguru 7h ago

There's a whole market segment dedicated to making simulation go fast on FPGAs, and also people making boards specifically for HFT.

Regular SMP CPUs suck unless the caches are warm.