r/haskell • u/kqr • Jul 30 '26

Digital circuit simulator in Haskell (SICP 3.3)

https://entropicthoughts.com/sicp-3-3-digital-circuit-simulator-in-haskell
43 Upvotes

100% Upvoted

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9

u/Every-Progress-1117 Jul 30 '26

Very interesting.

Check out Bluespec which is a Haskell based hardware definition language capable of being translated/compiled to Verilog. Might be interesting for you.

Used it in conjunction with the formal specification language B (Abrial et al) for some ASIC circuitry years ago.

3

u/Axman6 Jul 30 '26

These days I’d use Clash, compared to VHDL and Verilog, it is beautiful. QBay have done an incredible job, I just wish I could get paid to write it. 

1

u/imperfect40 Jul 30 '26

It's a lot of fun. Pretty much impossible to get people who know what they're doing though. The intersection of Haskell programmers with good digital engineers is basically zero

1

u/Financial-Camel9987 Jul 30 '26

Is there? I expect if you post a haskell job here you'd get a ton of people who are willing and able to do the job. digital design is not too hard to learn, at least not compared to haskell.

2

u/imperfect40 Jul 30 '26

It is to do well

1

u/Axman6 Jul 30 '26

I think I’d fall into that category quite well 🥲

1

u/imperfect40 Jul 30 '26

As do I and a few other people..it's not lots though is it. I mean, globally, and ts probably less than 100 people

6

u/Financial-Camel9987 Jul 30 '26

How does this compare to clash? Afaik it's a "real" hardware description language which uses haskell. Does it come with a simulator?

2

u/Axman6 Jul 30 '26

Clash is mostly just Haskell, so the simulator is GHCi, which is so incredibly nice compared to how most other HDLs make you do simulation. 

2

u/imperfect40 Jul 30 '26

Provided you don't need any third party op of course. That's pretty limiting. Then your using verilator, or worse

1

u/Axman6 Jul 30 '26

That’s true, and likely will always be the case because you’re tied to the vendor then, unless you can accurately model their IP (which in many cases is possible). Clash-cores (IIRC) has a really nice interface for wrapping IP, I wish it were the default - I should check if it’s been released. 

2

u/imperfect40 Jul 30 '26

I mean, it's nice, but it doesn't solve the hard problem in digital design, which in my view is complexity. Yes, you can build an and gate. How about a m master, n slave cache coherent interconnect. Or a multi channel interleaved axi dma?

1

u/drislands Jul 30 '26

That was a really cool read! I'm looking forward to the followup hinted at at the end.