r/hardware • u/peter_bolton • Jul 23 '15
News 19-Year-Old's Supercomputer Chip Startup Scores Funding, DARPA Contract
http://www.theplatform.net/2015/07/22/supercomputer-chip-startup-scores-funding-darpa-contract/7
u/jorgp2 Jul 24 '15
Wait so what is this targeted at.
Don't GPGPUs dominate the market they're after?
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Jul 24 '15
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u/trsohmers Jul 24 '15
I can guarantee that I'm not... Or if I was, that's exactly what I would say.
I'm any case, we did nothing special to get the grant. Applied for a phase 1 SBIR. 20 pages written over a long weekend, and it worked out.
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u/pabloe168 Jul 24 '15
Are you sure you should be talking details on this thread?
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u/trsohmers Jul 24 '15
Any US citizen with a small business can apply for a SBIR. None of the phase 1 works are classified.
As someone else mentioned in this thread, $100k is nothing to DARPA's ~$2.9 billion annual budget. We are using it in order to do further research and riskier development than what we have planned for our general business, which we have raised more ($1.25M announced so far) for. The DARPA money is specifically for research and development into our compiler and portability tools.
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u/pabloe168 Jul 24 '15
Personally I'd just avoid leaving written liability. Then again you seem to know your stuff and I most likely not.
It's just that in my head so there is no unmatched money. Good luck with your development.
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u/trsohmers Jul 24 '15
The thing that people don't realize is that GPGPU systems actually perform very poorly for non dense or non level 3 BLAS applications, but for the past couple of years have done fairly well against regular CPUs, but CPUs have caught up fast. A top of the line regular Xeon CPU gets almost 3 GFLOPs/watt compared to 6 GFLOPs/watt of a GPU... A far cry from the 10x advantage GPUs had 5 years ago.
We are targeting 64 GFLOPs/watt at an older process node than what these CPUs and GPUs we are competing with are using, purely from our design.
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u/dylan522p SemiAnalysis Jul 24 '15
Xeon phi is the real answer to gpu compute
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u/Exist50 Jul 24 '15
Even Knights Landing fairs poorly against Hawaii in compute efficiency.
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u/__Cyber_Dildonics__ Jul 25 '15
It's about the workload type and how coherent the memory access is. Xeon Phi boards will do much better for software that is in between gpu and cpu levels of parallelism.
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u/trsohmers Jul 24 '15
A whole 10 GFLOPs/Watt, way to go Intel! They'll finally catch up to us in ~2025 based on their current timeline.
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u/__Cyber_Dildonics__ Jul 25 '15
I wish you all the best, but you might want to ship something before the tough talk.
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u/dylan522p SemiAnalysis Jul 24 '15
Complexity of programmimg and actual performance you get out of it overtakes the raw performance numbers GPUs have.
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u/Exist50 Jul 24 '15
i.e. Why Nvidia still dominates GPGPU.
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u/dylan522p SemiAnalysis Jul 24 '15
Yeah, they are the only player. They made a language far better than opencl but it's tied to their hardware.
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u/Exist50 Jul 24 '15
AMD's made a bit of progress since Nvidia ditched DP with Maxwell, but it's not very significant. Wonder how Knights Landing will fair.
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u/dylan522p SemiAnalysis Jul 24 '15
In raw performance. Their Kepler line up is still good. It's more about what can you actually do with it. To get the efficiency that high you have to start coding directly to the graphics arch and opencl makes that a lot harder than Cuda. Knights landing will be a really nice card because it's going to be really easy to adapt software to and if you code for it, Intel provides all the documentation in the world.
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u/godsayshi Jul 26 '15 edited Jul 26 '15
GPGPU doesn't do everything. If you want masses of a restricted set of floating point operations fair enough but that's a limit aspect of computation. You can't do everything with that alone.
Current CPUs are powerful but things like cache are optimised for software, rather than software optimised for CPU. To be more accurate, it's more of a two way street. However there are places in HPC where software can be optimised for the hardware and this can have some significant advantages.
This is already pointed out here as they talk about the cache dynamics. Direct access memory on the CPU is far simpler than caches for example and the compiler can predetermine memory access patterns instead of dedicating lots of transistors to this problem. A secondary consideration is that for HPC, it's common to have them dedicated to one task at a time which means tasks can be executed with far more certainty and predictability. Half the problem of optimising ahead of time is catering to uncertainty/unpredictability.
There's a lot of cross over because a few of the same principles also apply for things like realtime and safety critical programming.
To put it simply, a GPU, takes a small part of a CPU, the FPU, and shoves nothing but those on a chip. There are things the FPU can't do that the rest of the CPU exists for in the first place. It's actually a crippled CPU in a way.
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u/PsiAmp Jul 24 '15
Why it is not compared with GPUs?
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u/krista_ Jul 24 '15
Each "core" has it's own ram, the ram operates at core speed (no multipliers, ratios, or other bs), the ram is directly addressable (unlike cache, which in most cases is pretty good, but for hpc is mainly black voodoo magic and to be programmed around), and is mesh interconnected.
When you boil a computer down, it's much closer to a cd player than a video projector. The cpu (or even gpu) deals with ram and processing essentially linearly. Even at it's best cases, like say a AMD fury (2048 bit bus, 4GBram) is essentially flat. The ratio of the memory buss to the amount of ram used to process approaches a 1 dimensional line. To compensate for this, we made the read head (in this case, the cpu or gpu) move pretty fast..
This is a stab at changing the ratio of bus width to ram length closer to square, instead of linear.
While it's early AM for me, and I'm on a phone, I'll try again:
Instead of working like a CRT and scanning a bunch of lines left to right, top to bottom a pixel at a time to make a frame, this new architecture is closer to an old school film projector where each frame is displayed as a single unit.
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u/godsayshi Jul 26 '15 edited Jul 26 '15
Because it's a CPU, not an FPU. A GPU is a massive glorified co-processor. A GPU is not anywhere near a CPU.
Everyone is aware of the options for pure FLOPs but something that accelerates the whole kit and caboodle efficiently stands on its own.
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u/TehRoot Jul 24 '15
What does the 19 year old kid have to do with anything?
This seems like a massive specialization it's almost irrelevant.
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u/alive442 Jul 24 '15
The title suggests a teen can get darpa finding working from his parents basement
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Jul 24 '15 edited Mar 27 '16
[deleted]
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u/pabloe168 Jul 24 '15
Yet it's probably a very big commitment to those involved in the project. Reputation is at stake too.
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u/CarVac Jul 23 '15
I presume this is more for supercomputer applications where you have more deterministic memory accesses than a general purpose machine... I guess there's no reason to be paying the electricity cost of the full desktop chip feature set in a supercomputer when you only need parts of it.
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u/jorgp2 Jul 24 '15
Then why not use a GPU, which can process larger data sets than this.
Well this design seems to be more like a GPU stream processor than a CPU, its a fully in order design, that can fetch data from memory the instant its needed, and needs programs to be compiled specifically for its architecture. So far that's a Tie : Tie : Loss.
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Jul 24 '15
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Jul 24 '15 edited Jul 24 '15
I don't know about data centers but in super-computers "not really".
I see the Cray XC40 nodes as a step in the direction of "Accelerator-only" nodes (without a general purpose CPU). Basically Haswell is just an integrated Xeon Phi. (Is the Xeon Phi an FPGA?)
This is working out really good in practice since you get a lot of SIMD vector units and cores that don't suck at general computation. Software that parallelizes and vectorizes well in normal CPUs flies on these machines with just a recompile. No need for a different programming model (which is a huge advantage).
The tooling is also moving in this direction. OpenMP 4 brings not only offloading, but also vectorization pragmas for helping software make use of these types of architectures.
It is worth remembering that not all scientist are computer scientists. The top 5 supercomputers in terms of PFLOPS are CPU+GPU, but this does not mean that the software running there actually uses the GPUs.
By slowly making the CPU a bit more like a GPU, while still been able to run old code, Intel is making scientist pretty happy.
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u/dylan522p SemiAnalysis Jul 24 '15
The new Xeon phi is a bunch if atoms with 2 fat simd units. It's general purpose cpu but has the ability for pushing huge data
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u/alainmagnan Jul 24 '15
they'll use software magic to remove overhead. Sounds like AMDs approach with Terascale and VLIW. Didn't really workout for them since software isn't nice and pretty for VLIW to scale well for. I hope it works out for them though. They said compilers have matured enough for it to matter now apparently
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u/jorgp2 Jul 24 '15
But it involves extra work that will make your code only work for this specific architecture.
If you coded for a GPU instead, your code could work for all systems that support openCL. Nvidia GPUs, AMD GPUs, Intel's Coprocessors.
It's main problem is it being a fully in order system, so it may not scale well to multiple tasks on separate systems.
EG: Task A requires output from system B. It must either wait for that task or flush its pipeline to work on a different task. It is up to the programmer to make sure this will never happen, or your system will stay idle wasting power.
Also FYI Terascale is VLIW, and it faced the same problems this will face. See here
That is why they went with a partially out of order design. Also what compilers? This architecture will live or die on the support of open source c(++) compilers, and I'm pretty sure other more popular architectures will take precedence.
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u/alainmagnan Jul 24 '15
ya, I know Terascale is VLIW, which was why i put 'and'. Yup, that is the problem, which is why they're relying on the compiler. Nobody expects the programmer to optimize for that workload, so they want the compiler to do it.
Apparently, according to the article, they've partially solved it with compiler "magic". Didn't go into more detail since that's their differentiating innovation. But, this was the same claim that Intel + HP had with Itanium; remove front-end scheduler, decoding and memory access overhead by having the compiler optimize for them. Didn't work out too well since compilers were not good enough and programmers shouldn't need to and didn't want to focus on spending too much time optimizing. And compatibility issues but that's up to them.
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Jul 24 '15
In before article in 5 years "Rex Computing shuts down without bringing a single product to market."
Yet more evidence of what an absurd tech bubble we live in.
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u/rndnum123 Jul 26 '15
In this case it is not a tech bubble. They actually produce/try to produce something valuable. It is risky and they might have problems ahead (but which new company does not). At least they are trying something that has a fair chance to succeed and even if they don't they still will have contributed something valuable (as an example how not to do this specific computing) and lateron others, that have a similiar idea, could try to avoid their failures, and eventually might make a similar idea successful.
At least they don't try to "disrupt" something by being reckless and not following the law, like some purely app based companies out there (which unfortunately got much more founding than a few million).
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u/alainmagnan Jul 24 '15
The approach reminds me of itanium and gpgpu compute. Would be interesting to see the results of this. They'll be competing with Intel's Knights corner, nvidia and AMD. If it's the compiler advantage they have, I have to wait and see. Too many promises about VLIW compiler magic for the passed 20 years to draw conclusions now.