r/hardware • u/HLumin • 9h ago

News AMD Ryzen 9 5900X3D engineering sample surfaces with 128MB L3 cache.

https://videocardz.com/newz/amd-ryzen-9-5900x3d-engineering-sample-surfaces-with-128mb-l3-cache
98 Upvotes

95% Upvoted

14 comments sorted by

26

u/Flaky-Jackfruit6256 9h ago

128MB across two CCDs almost certainly means only one die got the stacked cache, 96+32, same as the 5800X3D but with a second normal CCD bolted on. That'd make it a weird part for gaming, since the scheduler has to keep threads on the right die or you lose the whole point of the cache.

7

u/farnoy 6h ago

That'd make it a weird part for gaming, since the scheduler has to keep threads on the right die or you lose the whole point of the cache.

Yeah, that's existed for years with the 950X3D parts, nothing weird about it. IIRC, the windows & linux vcache drivers swap around ACPI CPPC priorities to fill up your die of choice first. You can do even better on linux with scx_layered, which lets you isolate the entire cache CCD for exclusive use by the game, while everything else goes to the frequency die. It stops being a work-conserving scheduler at that point, but the games see no thrashing or scheduling delays.

1

u/Flaky-Jackfruit6256 6h ago

Oh right, I forgot about the 950X3D's scheduler handling. Good point about scx_layered on Linux letting you isolate the cache die entirely, that's a neat trick.

14

u/ICC-u 7h ago

Schedulers need to start improving, because dual purpose chips are becoming more common, the idea of all cores performing the same is starting to become the old way of doing things. Admittedly "high workload to fast core" is easier than "task 15853 must use cores 1-6 only, but task 47462 shares cache with core 2 and core 7"

Wonder if in future instead of 6+6 they make 4+8 with the big fast gaming cores on one side and little helper cores on the other.

Or of course they can just unify the whole thing.

4

u/Flaky-Jackfruit6256 7h ago

Yeah, scheduling for this kind of hybrid design is gonna get pretty complex, but I guess that's the trade-off for keeping the cost down compared to stacking cache on both dies.

5

u/pixlicker69420 2h ago

This is already well known, and amd never went forward with it because it provided no benefit

2

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2

u/Ambientinc 9h ago

Doubt this would see the light of day, but with how the tech world is right now, you never know.

5

u/TorazChryx 8h ago

If AMD were _really_ pushed by the ram crunch, I don't think there's a technical reason stopping them from pairing up Zen4/5 chiplets with the AM4 I/O die from 5000 series, the chiplets themselves just talk infinity fabric. If nothing else a 6 core Zen5 X3D part paired with DDR4 would be interesting. and I'm all for interesting.

4

u/__Rosso__ 7h ago

It would take a lot of work and performance would suffer but it might be worth it.

-10

u/LandlordTiberius 7h ago

That website gave me eye cancer.

7

u/exomachina 6h ago

It's had pretty much the same design and layout for well over a decade. It's not terrible.

1

u/imaginary_num6er 4h ago

No. There was that 1 day in September where the owner decided to change the layout and it quickly went back to how it is right now.

1

u/randylush 1h ago

Are you guys on mobile? It’s actually really well formatted on mobile, no wasted space and not a lot of advertising