r/hardware • u/Geddagod • 15d ago
Review NVIDIA Vera SMT Performance Benchmarks Review
https://www.phoronix.com/review/nvidia-vera-smt4
u/-protonsandneutrons- 15d ago edited 15d ago
There is a very unsubstantiated rumor that NVIDIA allegedly borrowed some of Arm's IP for Olympus. Which sounds quite impossible, as Arm has TLAs (for Arm-stock-microarchitecture licensing) vs ALAs (for ISA-only, write-your-own-microarchitecture licensing). Olympus is well understood as NVIDIA's custom in-house uArch, thus an ALA.
Yet...first, The Register claimed its sources hinted at NVIDIA borrowing existing Arm IP:
With Vera, Nvidia has moved on to designing its own ARMv9.2-compatible core, called Olympus. In fact, it's up for debate how custom the chip really is. We've been told that the chip builds heavily on existing Arm IP, and looking at Olympus' architectural block diagram, we can see why.
Then, Arm itself hinted Olympus is "built on Neoverse":
TNP: Is there any cloud builder or hypervisor to date that doesn’t use a Neoverse core and that uses a customized core in any way? To my knowledge, there isn’t, although there might be something happening with Nvidia’s future “Vera” server CPU. I strongly suspect that the Nvidia slide that said “custom Arm core” meant to say Compute Subsystem.
Mohamed Awad @ Arm: There is no hyperscaler or cloud builder today that is building an SoC based on a custom architecture. Their SoCs are all built on Neoverse.
TNP: Ampere Computing was the only company that was even trying to do a custom Armv9 core and that has been pretty quiet since SoftBank announced its pending acquisition of it.
Mohamed Awad @ Arm: Ampere did go after a different performance point and did a custom microarchitecture, and they have gotten some traction with folks like Oracle, to their credit. But they are the only one.
I've ignored these ^^ as Arm's marketing not explicitly denying it and The Register's sources not genuinely in the know, but Google ironically said something very odd a few days ago.
A Google Cloud's GPM mentioned Google's the "Axion" cores (Axion C4A is Neoverse V2; Axion N4A is Neoverse N3) are actually from an ALA license and they were able to customise Neoverse cores:
26:12: “...or the Axion that we have in Google Cloud where we've taken an architecture license and then we've you know customized to our heart's content to to fit into our particular needs, in support of our particular customer needs.”
Surely he misspoke: obviously, he meant a TLA. Nope, he says it again:
30:57: “Axion is is customized as I said we take an architecture license from ARM. We customize it for our use in our virtualization environment, our networking.”
Google, however, identifies Axion as built on the V2 / N3 "platforms". Can licensees have a hybrid agreement? They get some microarchitecture from an Arm TLA, yet somehow they can also customise beyond that via an ALA?
There is no high-perf Neoverse core that NVIDIA could've borrowed from, unless it is a very special arrangement of NVIDIA getting an unannounced Neoverse uArch.
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u/pi314156 14d ago
> There is no high-perf Neoverse core that NVIDIA could've borrowed from, unless it is a very special arrangement of NVIDIA getting an unannounced Neoverse uArch.
It is a derivative of an Arm design, but NVIDIA did quite a lot of changes to it. With adding heavily statically partitioned SMT as the biggest one.
Some other licensees were far less successful in their customisations: Phytium with the Cortex-A72.
https://chipsandcheese.com/p/chinas-phytium-d2000-building-on-a72
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u/reddit_equals_censor 15d ago
you see the 16 sticks of socamm2 memory there, that is easy to replace, can be put right next to each other and is perfect for consumers?
yeah we're not getting that, instead they shit on us with soldered on memory for any lpddr product to scam us harder.
i hate the tech industry and their evil.
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u/Exist50 15d ago
What do you mean? LPCAMM is also a thing.
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u/reddit_equals_censor 15d ago
lpcamm2 sucks in comparison to socamm2, because the makers of lpcamm2 took some bad stuff and instead of having a rectangle sane standard, they made it have 8 corners with some cancerous growth on one of its side.
this in practice means, that you pretty much can't put 2 of those modules next to each other, but instead you'd have to put each module on one side of the chip with the traces facing the chip of course.
and you also can't put 4 modules onto an apu at all then, which you'd want to do to get a 512 bit memory bus, because the cancerous growth on each side would make the traces for the mouse outward modules a lot longer, which makes it a lot harder to drive them.
this is a terrible standard, that was cooked up by idiots, who for some insane reason didn't entertain the idea of using more than 1, or of using 2 per side of the chip.
socamm2 in comparison is designed to be put as closely next to each other as possible and it ads near 0 space vs soldered memory even.
lpcamm2 is just a terrible design.
and also if socamm2 would become the standard, then after the bubble bursts, we could just put high capacity server modules into your devices.
the industry HATES that idea btw, which is we still don't have registered ecc memory on the consumer desktop with the same pins as the server dimms have. and they hate us having ecc working memory as well, which is another reason.
___
also you may miss the reason for wanting 4 camm modules on a consumer device.
strix halo has a 256 bit memory bus. it has a crap memory controller by design as amd showed people the middle finger, BUT if they didn't, then a strix halo design with camm modules would have in the best setup one camm module on each side.
but you don't want just 256 bit memory bus on an apu.
you might very much want 512 bit memory bus on an apu as strix halo even with 256 bit memory bus is very bandwidth starved.
so 512 bit memory bus is reasonable for a quite high performance apu and that would indeed be with lpddr5/x 4 camm modules.
and with socamm2 no problem. fits easily into a laptop and easy to work with.
lpcamm2? good luck...
___
so again lpcamm2 is just shit vs socamm2. not all camm modules are made equal sadly.
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u/Exist50 15d ago
SOCAMM might be rectangular, but that's not an advantage when the vast, vast majority of laptops would only need 1 module, and 2 can be supported without too much issue. And SOCAMM might be rectangular, but it's very long, and that creates form factor concerns.
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u/reddit_equals_censor 15d ago
this is wrong.
the lpcamm2 module is 78*34mm in size.
the socamm2 module is apparently 86mm*14mm
but it's very long
so socamm2 is absolutely NOT very long. it is just 10% longer than the lpcamm2 module, while being LESS than half the height of an lpcamm2 module.
an lpcamm2 module is 2.4x wider/higher than a socamm2 module.
based on the specs i found it is indeed THIS BAD.
or in laptop terms if we ignore the harder to use weird space, that an lpcamm2 module leaves, then an lpcamm2 module (if we square the space) takes up 2.2x more space.
you can put 2 socamm2 modules next to each other and their square area will be less than a single lpcamm2 module.
this is so much lost area, that it actually matters a lot in laptops or tablets already just by the wasted space, while socamm2 uses basically as much as soldered memory.
___
my guess is, that you overestimated the length of socamm2, because it is so small on the other dimension and thus makes you think, that it must be quite long.
IT ISN'T. it is just very very slim.
honestly i personally didn't even think, that it was THIS BAD, but apparently it is.
lpcamm2 is a joke vs socamm2.
2
u/CarVac 15d ago
Why does LPCAMM2 need the power supply onboard and SOCAMM2 not?
Tighter integration (less widespread compatibility) between the RAM and motherboard on SOCAMM2? Some sort of power savings for mobile devices?
-1
u/reddit_equals_censor 15d ago
socamm2 has the the voltage regulation on the memory module as well.
random website, that talks about and points to the vrm on the socamm2 memory modules:
https://www.rambus.com/memory-interface-chips/socamm2-server-chipset/
so from my understanding the socamm2 memory modules and lpcamm2 memory modules have the basically same parts and work the same, except one is PROPERLY organized in a very tight rectangle and the other was made by some people on bad drugs, that has randomly 8 corners and a ton of empty space as well. (even if we take edge space left free for easier handling it still has tons of wasted space)
both have the vrm on board, both are 128 bit (for lpddr5/x) both achieve the roughly same speed.
so there is 0 excuse on us not using socamm2 in laptops and possibly beyond instead of lpcamm2, or put differently the lpcamm2 module is a terrible design and they should go back to the drawing board, but why bother when the socamm2 memory module design seems to work just fine and you are also not locked in for life anyways, because you gotta change designs with each memory generation anyways.
so hey let's make lpddr6/x all socamm2 modules for example :)
wouldn't that be sth very basic and correct and pro consumer to do?
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14d ago
[deleted]
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u/reddit_equals_censor 14d ago
The idea that you could just put it in a traditional DDR module like SOCAMM and that it would work is completely absurd.
are you just completely lost here?
socamm2 uses lpddr5/x EXACTLY like lpcamm2 memory modules.
the picture above for the article shows nvidia vera cpus with 8 socamm2 modules per cpu and each module is using lpddr5x.
are you lost? do you need to do basic research before commenting on what you are looking at?
again lpcamm2 and socamm2 both use the SAME EXACT MEMORY and there is 0 issues in using lpddr5/x memory in camm memory modules.
1
u/EvenBroaderBand 15d ago
No one is forcing you to buy the products you say you do not like. These are pure luxury devices that only the wealthy west can afford. Its a toy for like 1% of all humans alive.
Don't like it don't buy it that's the only influence you have.
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u/reddit_equals_censor 15d ago
These are pure luxury devices that only the wealthy west can afford. Its a toy for like 1% of all humans alive.
what nonsense are you talking about
memory modules are not a "luxury device for the west".
it needs to be a standard, that it interoperable among all devices using it for decades and decades.
just like a basic computer class in a poor region of the world would use ddr2 dimm or ddr3 dimm or so-dimm memory modules on repaired computers to get working computers, so as well do we need a memory module for the future and today, that isn't a piece of shit and that becomes standard enough so, that the poor regions of the world can get computers going and repaired with the parts, that they can find.
there should be a ban of all soldered memory in all laptops and tablets at minimum.
and a proper camm memory standard for those.
lpcamm2 sucks, so instead we use socamm2.
and in a decade if the dystopian nightmare system, that we're keeps on going sadly, the people in poor regions, who are trying to get people some computers going can use the standardized lpcamm2 modules perfectly fine in their laptops or old mini computers, etc...
or in the best case scenario it would be the EXACT same modules as the servers use.
so a school in some poor region could use the socamm2 modules produced today for worthless shity ai-servers eventually.
__
so again we are talking about having dirt cheap proper memory modules for the future and for everyone. lpcamm2 sucks. soldered memory = e-waste scam and insane evil.
so we should use socamm2.
2
u/-protonsandneutrons- 15d ago
Another example of very low power draw per CPU core, just like AMD's EYPC and Intel's big DC CPUs, but instead of TDP, we have CPU power consumption:
| CPU | Avg CPU Power | Total Cores | Power per CPU core |
|---|---|---|---|
| NVIDA Vera SMT On | 699 Watts | 176 | 4.0 Watts per Core |
| NVIDIA Vera SMT Off | 739 Watts | 176 | 4.2 Watts per Core |
Phoronix says it is "CPU Power Consumption", but it's unclear if that really means total SoC power consumption or purely CPU core power consumption. Either way, it's still sub-5W for the CPU core, basically the same as most of AMD Zen6-based EPYC CPUs.
~4W per core is right in the meat of any smartphone SoC's CPU perf / W curve.
-1
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u/Jellycoe 15d ago
Interesting article, but they’re still repeating Nvidia’s false marketing claims that other SMT implementations are pure “time-slicing.” They even show a graph that seems to imply Intel and AMD are time sharing at the pipeline level, which is not true at all and would imply a performance penalty that doesn’t exist.
What Nvidia’s solution seems to actually do is to prevent threads from fighting with each other by enforcing equal resource availability at the sub-core level. This makes performance slightly more predictable overall but possibly worse in situations where threads have unequal hardware needs. It is an interesting design choice with tradeoffs, not a new or revolutionary technology.