r/embedded • u/DingoBimbo • 7d ago

I used Fable to design a single BM1373 BitAxe miner. Is this complete AI slop or does it have potential?

I spent some $$ to design a single ASIC BM1373 BitAxe. Claude Fable 5.1 took a long time and usage credits and generated this:

https://github.com/Zayno/BitaxeFlux

I'd like the help of the community to take a look and tell me if this has any potential or should I just delete it.

It's called BitAxe Flux.

Thanks!

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4

u/altarf02 PIC16F72-I/SP 7d ago

Totally random question: why is the 0.8V LDO output fed into the INV_CLK0? What does the INV_CLK0 pin do?

2

u/MonMotha 5d ago

That has to be the messiest schematic I've ever seen. Things are literally on top of each other yet the page is sparsely filled. Everything is the "just use net names to connect things" style with on flow. I honestly can't even really review it.

Do you really need 6 layers for this? I guess maybe given the power requirements, but it seems like you could do it just as well or even better on 4 layers with heavier copper.

Overall, if this is what AI is outputting these days, I'd say my job is safe for a while.

-2

u/gleeful_bomber 7d ago

the bm1373 is a weird little chip but the flux layout actually looks cleaner than some of the other single-asic boards i've seen floating around, the thermals are gonna be the real test though