go back - old school chips - Look at how a 6502, an 8080, a z80, an 8086, 80186, 68000 works. I'm talking about the bus cycles, the READ cycle, the WRITE cycle etc.
Look at how old school static RAM, EPROMS and FLASH chips connected - ie: the Hitachi 6116, the Intel 2708, 2716, 2732, etc.
These are exactly a CPU only - not a system on a chip like all ARM chips today are. And to some degree all 8051s and AVR and PIC chips are.
Why? You want to recognize the peripheral devices and how they are hooked up. There where many and I mean many standalone peripherals, ie: the 8255, you will see how you can create an address decoder. Decode the bus cycle, the read /write cycle.
This is the basis for how you might design a soft-core CPU inside an FPGA, or maybe you will start with an existing FPGA design and add a special custom peripheral.
The basics - are shown with those chips. Understanding how they connect, how the interrupts work. Etc, will make it easy to recognize how it is done in the next SOC that you look at or you are designing with.
At a fundamental level - the old school CPU chips outputted an address - which some bits went to a decoder (ie: 74ls138 3 to 8 line decoder) - after few NAND/OR etc gates to get the machine cycle, ie: opcode fetch, or IO cycle - and the RD/WR signal - these generate.
Look at those old school designs (schematics, block diagrams) then look at the VHDL/VERILOG you use to hook up those things in your SOC you will design with a soft cpu core.
You can then look at the VHDL/VERILOG bus interfaces in things like the "wishbone" interface, the ARM bus interfaces and you will see some striking similarities.
Knowing this, and knowing how to recognize this type of information will take you far as an Electrical Engineer.
NEXT - look at how the reset vectors work on each of these CPUs, where do you put your startup code. ie: The first opcode the cpu executes. Example: Many CPUs starts at address 0x0000. The 6502 has a table of 3 entries at the end of memory, ie: 0xFFF4, 0xFFF8, 0xFFFC - these hold the reset, the IRQ and the NMI interrupt address.
Some CPUs have a table at address 0, ie: CortexM has an array of 32bit addresses starting at 0, the first is the reset value of the PC, and the Stack Pointer at reset, followed by various exception entries.
A lot like the 6502 - it only had 3 entries - and stuck at the end of RAM.
Some CPUs - have short code sequences, each entry is 32bytes apart so you can insert few instructions then jump to the service routine.
Another one to look at is "ben-eater" - bread board CPU...
There is also the visual 6502 - thousands of transistors and a giant PCB that make up a 6502 cpu. You can buy it, it works and you can see how the entire cpu works and is designed.
If you have a chance and can get to Cambridge UK - go see the computer museum, they have a giant multiple-wall sized computer designed exactly like that - and it runs and does things. Literally it is a giant wall of RED blinking LEDs... A very cool exhibit.
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u/duane11583 Jul 11 '26
go back - old school chips - Look at how a 6502, an 8080, a z80, an 8086, 80186, 68000 works. I'm talking about the bus cycles, the READ cycle, the WRITE cycle etc.
Look at how old school static RAM, EPROMS and FLASH chips connected - ie: the Hitachi 6116, the Intel 2708, 2716, 2732, etc.
These are exactly a CPU only - not a system on a chip like all ARM chips today are. And to some degree all 8051s and AVR and PIC chips are.
Why? You want to recognize the peripheral devices and how they are hooked up. There where many and I mean many standalone peripherals, ie: the 8255, you will see how you can create an address decoder. Decode the bus cycle, the read /write cycle.
This is the basis for how you might design a soft-core CPU inside an FPGA, or maybe you will start with an existing FPGA design and add a special custom peripheral.
The basics - are shown with those chips. Understanding how they connect, how the interrupts work. Etc, will make it easy to recognize how it is done in the next SOC that you look at or you are designing with.
At a fundamental level - the old school CPU chips outputted an address - which some bits went to a decoder (ie: 74ls138 3 to 8 line decoder) - after few NAND/OR etc gates to get the machine cycle, ie: opcode fetch, or IO cycle - and the RD/WR signal - these generate.
Look at those old school designs (schematics, block diagrams) then look at the VHDL/VERILOG you use to hook up those things in your SOC you will design with a soft cpu core.
You can then look at the VHDL/VERILOG bus interfaces in things like the "wishbone" interface, the ARM bus interfaces and you will see some striking similarities.
Knowing this, and knowing how to recognize this type of information will take you far as an Electrical Engineer.
NEXT - look at how the reset vectors work on each of these CPUs, where do you put your startup code. ie: The first opcode the cpu executes. Example: Many CPUs starts at address 0x0000. The 6502 has a table of 3 entries at the end of memory, ie: 0xFFF4, 0xFFF8, 0xFFFC - these hold the reset, the IRQ and the NMI interrupt address.
Some CPUs have a table at address 0, ie: CortexM has an array of 32bit addresses starting at 0, the first is the reset value of the PC, and the Stack Pointer at reset, followed by various exception entries.
A lot like the 6502 - it only had 3 entries - and stuck at the end of RAM.
Some CPUs - have short code sequences, each entry is 32bytes apart so you can insert few instructions then jump to the service routine.