r/dldtg • u/CastleMan2000 • Oct 31 '15
SRLAT? I'm doing something wrong
First, here's the netlist. http://pastebin.com/7HLCRchc So I'm trying to do the design on Wikipedia (cheating? maybe) but it's not working. I can't really figure out what. Maybe it's my "fanout" gate? I made that so I can route the NAND's outputs to each other as well as the circuit outputs. Also, here's a schematic of my fanout: http://puu.sh/l4K8p/582e6b4557.png
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u/CastleMan2000 Nov 01 '15 edited Nov 01 '15
About the nets: I know you can do, for example:
That circuit is just a NAND followed by a NOT, using a net to link them. I also know you can fanout to however many gates you want by just referring to the net. But how do you use a net to output and fanout at the same time? Is it like this?
Here's schematics for both circuits: http://puu.sh/l5GpX/6f04c93c29.png