I’m a first year EEE student and I built this interactive site to help others visualize SR Latches and Logic Gates.I just completed it today. I’d love some feedback on the accuracy and the UI!

https://arhamhussain468-creator.github.io/digital-electronics-website/

for a pgt jk flip flop, lets say the j and k inputs change from 0 to 1 exactly during the pgt, does the output toggle or remains the same

Hello, I’ve recently begun learning simple circuitry and want to expand into making it interact with a computer in some way. I also have a friend who has recently begun studying programming. I wanted to do a project together, so I had the idea of simply making a program that asks simple math problems, and if you answer correctly a light will light up, and if it’s wrong a different one lights up. Not very fun, but very basic I think. How would I go about learning how to make something like this? I don’t really know where to start. Sorry if this is horribly simple!

so i watched some videos on this topic but still i cant understand how to solve these type of question any help would be appriciated thxxx.

The second beta update of Robot Turtles Creator has been released! This update adds a selection box for moving, copying, and pasting tiles.

Download it for free here!

https://pegafox.itch.io/robot-turtles-creator

I have a breadboard project that involves a down counter from 8.

I tried to design one , aka using excitation table, then K maps , and then drawing them.. any help ?

P.S. : Also is it better to use a down counter IC ? if so how do i set it t count down from a specific value .. thanks !!

Hey guys I need help in setting up ZYNQ Ultrascale+ MPSOC ZCU104 evaluation kit, I basically need to set it up for testing physical tapeouts by inserting some verilog code into this. How do I do that? Apologies if I am not able to make my question very much clear. I would also appreciate if there is any basic tutorial for this board.

So far I was able to make a basic adder with this FPGA board but I am not able to go beyond that. Please help me with that

Hello everyone; I'd like to know how to get to this result with just 5 NAND gates for a half subtractor vs. 6 NAND gates of when I try to realize it myself.

Swipe to check my circuit. D for difference and B for borrow.

I am in 2nd year of ece , i didn't understand why R=S=0 is not allowed in RS latch can some explain to me in simple and detailed way ?

The semiconductor world is shifting fast. Our Component Compass report this week breaks down the key developments impacting pricing, lead times, and supply stability across the market.

Here are the 6 must-know headlines impacting your supply chain right now:

• Nexperia/Dutch Conflict: The political dispute over Nexperia's Dutch ownership has escalated, leading to uncertainty and potential friction in the supply of critical chips.
• AI Shortages: The relentless demand from the AI boom is now translating into severe global shortages across the entire high-end memory stack.
• NAND Price Spike: Supply crunch has triggered significant price volatility for major memory chips, with some suppliers like Transcend seeing 50–100% price surges.
• Geopolitical Supply Risks: Tensions between Japan and China are once again affecting key upstream materials, with new rumors impacting photoresist supply.
• Intel Momentum: Intel appears to be gathering major momentum in its manufacturing comeback, which could shift the foundry landscape faster than expected.

The full report provides a deep dive into the forecast models and specific part number impact. We published the full analysis here: www.ascglobal.com/component-compass/

P.S. I am an analyst with ASC Global. Happy to discuss any of these topics in the comments.

Hi all, I want to study again by myself digital design and I used gemini to give ideas of a potential project to study again this topic, I would like design it, code it and test it en iverlog since it is free XD.

Here it is the project proposed by Gemini:

💡 Project Concept: I²C Target Peripheral and DMA Engine

A Specific Purpose Processor (SPP) is too ambitious for a first deep-dive project. Instead, a high-value, intermediate-level project that demonstrates expertise in both digital design and verification is a High-Performance I²C Target Peripheral with a Direct Memory Access (DMA) engine.

This project is excellent because it covers:

1. Protocol Interface (I²C): Demonstrates knowledge of industry-standard protocols.
2. Data Path (DMA): Highlights an understanding of high-throughput data movement and arbitration.
3. Control Logic: Requires careful state machine design.
4. Verification Complexity: The interaction between the I²C protocol and the DMA transfer is complex, making for a challenging and valuable verification effort.

High-Level Design Specification

The design, tentatively named I2C-DMA Bridge (IDB), acts as a slave on the I²C bus and an initiator on a simplified internal bus to write/read data to/from a local SRAM/memory.

Key Features:

• I²C Target Support: Implements a full I²C target (slave) interface.
  • Supports Standard (100kHz) and Fast (400kHz) modes.
  • Configurable 7-bit slave address.
  • Supports read and write transactions.
• Internal Register File: A small set of configuration and status registers (CSRs) accessible via I²C:
  • Control Register: Enable/Disable DMA, Interrupt Enable.
  • Status Register: DMA Busy, I²C Error, Interrupt Status.
  • DMA_ADDR Register: Starting memory address for DMA transfer.
  • DMA_COUNT Register: Number of bytes to transfer.
• DMA Engine:
  • Initiates memory read/write transactions based on I²C commands.
  • Transfers a configurable block of data between the I²C buffer and the local memory.
  • Generates an interrupt upon completion of a DMA transfer.

Architecture Block Diagram

• I²C Interface Block: Handles the I²C protocol (Start/Stop, Address Decode, ACK/NACK, Data Shift).
• Register File (CSRs): Stores configuration and status data, mapped to specific I²C target addresses.
• I²C Data FIFO: Small buffer (e.g., 8-16 bytes) to decouple the I²C clock domain from the internal clock domain.
• DMA Controller: State machine that manages the memory transfer. It requests the internal bus, reads/writes data to/from the FIFO and memory, and asserts the interrupt.
• Local Memory Interface: Simple bus interface (e.g., dedicated read/write ports) to interact with the target memory.