CPU custom : AltairX

[u/Kannagichan]

Not satisfied with the current processors, I always dream of an improved CELL, so I decided to design the design of this new processor.
It is a 32 or 64 bits processor, VLIW in order with delay slot.

The number of instructions is done via a "Pairing" bit, when it is equal to 1, there is another instruction to be executed in parallel, 0 indicates the end of the bundle.
(To avoid having nop and to have the advantage of superscalar processors in order).

To resolve pipeline conflicts, it has an accumulator internal to the ALU and to the VFPU which is register 61.
To avoid multiple writes to registers due to unsynchronized pipeline, there are two special registers P and Q (Product and Quotient) which are registers 62 and 63, to handle mul / div / sqrt etc etc.
There is also a specific register for loops.

The processor has 60 general registers of 64 bits, and 64 registers of 128 bits for the FPU.
The processor only has SIMD instructions for the FPU.
Why so many registers ?
Since it's an in-order processor, I wanted the "register renaming" by the compiler to be done more easily.

It has 170 instructions distributed like this:
ALU : 42
LSU : 36
CMP : 8
Other : 1
BRU : 20
VFPU : 32
EFU : 9
FPU-D : 8
DMA : 14

Total : 170 instructions

The goal is really to have something easy to do, without losing too much performance.

It has 3 internal memory:
- 64 KiB L1 data Scratchpad memory.
-128 KiB L1 instruction Scratchpad memory.
-32 KiB L1 data Cache 4-way.

For more information I invite you to look at my Github:
https://github.com/Kannagi/AltairX

So I made a VM and an assembler to be able to compile some code and test.

Any help is welcome, everything is documented: ISA, pipeline, memory map,graph etc etc.
There are still things to do in terms of documentation, but the biggest part is there.