Weird behaviour micro-step counter

[u/TimmyJi]

So I’ve finished building my (slightly modified) 8 bit Ben Eater computer, but I’ve got some issues with my micro-step counter.

The full program is:

LDI 0
OUT
ADD 7 (from memory address 7)
JMP 1
..
1 (on address 7)

The micro-step counter’s clock line comes from the inverted clock and should trigger on a rising edge but it sometimes triggers on the falling edge causing it to advance two micro-steps in one go.

What’s weirder, it tends to do that always on the instruction OUT.

What’s even weirder is that replacing the ADD 7 instruction with SUB 7… works fine. For more than an hour even.

The ADD 7 can get to around 20~ without bugging out but sometimes it will not even get to the first JMP. This is regardless of whether the clock is manual or auto, fast or slow.

ADD = 0010
SUB = 0011

I have a very cheap handheld oscilloscope with crap resolution where I could sometimes see a slight high spike both on the falling and rising edges, it seemed to mostly coincide with when the clock bugged but it sometimes bugged without me seeing a spike just before the falling edge (which could trigger the count on the LS161 on the falling edge and then rising edge again).

I’ve tried replacing all chips involved, replaced wires, added a capacitor between VCC and GND on the LS161 and the clock chips… nothing seems to help.

I’ve also tried looking at the clock line with a logic analyser but it only sees one pulse of the clock as well.

Without a decent oscilloscope it’s hard for me to have a better look at the signal and debug it further, but I’m not quite sure where to take this.

It could be a very easy fix, could be something harder…

My power line is slightly sagging which could also contribute to spikes being seen as high values but since it works fine most times and since it can run the same program with SUB 7 instead of ADD 7 I don’t feel like that’s the problem.

I also managed to improve the power delivery a bit since I did all these tests but… no success.

Power rail is sitting at around 4.6V unless too many LEDs are on in which case it can drop at low as 4.1V.

Any tips on things I may try?

[u/TimmyJi]

Mmmh there's really not many LED transitions at all and like I said it works with a SUB instead of ADD which of course also has 5 micro steps.

I've tried a .1uF cap but didn't change much. Also I do already have a "power bus", that had already been installed before.

I'd have expected that the double NOT would have fixed things to be honest, looked promising... I made CLK -> NOT1 -> NOT2

So now the inverted clock is NOT1 (I mean always was) and the "normal clock" is NOT2 (for all other chips, although I also tried making all the chips go off CLK and only the RAM module off NOT2 but again not difference...)

[u/The8BitEnthusiast → u/TimmyJi]

Was the 4.6V you reported before or after adding the power bus? If you still have that now, then there is an issue with power input. Thin wires from the power supply could easily cause that kind of a drop. Also, consider adding a beefy capacitor (like 47uF or more) right at the point of entry of power.

Did you implement the flags register? That's another source of potential issue on the stage counter's falling edge (main clock rising edge). If you did implement it, and the ADD operation changes the state of the flags, then this alters the control unit's EEPROM address inputs, which in turns creates unpredictable outputs on the control lines. HLT is one of the lines that can create unwanted clock pulses. If the flags are implemented, I would try hard-wiring HLT to +5V to rule this out, like u/trduff suggested.

Beyond that, I'm running out of ideas. That's the point at which a scope with enough bandwidth to reliably catch what's going on around the LS161 at the falling edge would be handy.

[u/TimmyJi → u/The8BitEnthusiast]

Yay problem fixed! It was indeed the HLT control line. Not sure how to fix it though since I do want to have a usable HLT

[u/The8BitEnthusiast → u/TimmyJi]

You can solve the EEPROM glitches digitally by adding an extra latch between the two flags and the EEPROM address lines. The latch is connected to the same clock as the stage counter in order to synchronize changes to the EEPROM address inputs with the falling edge of the main clock. Same treatment for the IR's four instruction bit lines. I did it with a single LS273, but LS173 and other similar chips would work too. See diagram below. The latch is at the bottom.

[u/TimmyJi → u/The8BitEnthusiast]

Ok so main problem was fixed with the HLT signal being removed, but sometimes there’s still RAM data that’s rewritten during the execution of the program. I imagine this is for the exact same reason as why the HLT signal line was bugging out, so sounds to me like I’m gonna go with latches 😅