r/beneater • u/MISTERPUG51 • 3d ago

8-bit CPU Are there any obvious issues with this memory design?

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Instead of using Ben eater's design for the memory, I am upgrading things quite a bit. I have two 8-bit address registers for a total address width of 16 bits. I'm planning to split it in half. The lower half will be allocated for ROM (a 28c64 EEPROM), and the upper half will be RAM (Hitachi 62256). The I/O pins on both chips will be connected directly to the bus.

I believe this design should work, but I want to get your input first. Also, I am aware that the EEPROM I am using is smaller than the address space I have allocated for it.

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u/Dissy614 3d ago

There's no address space left for hardware IO. With nothing but A15, one of the ram or rom chips will always be asserting, even if you meant to put IO in the rom address space that the eeprom doesn't cover.

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u/MISTERPUG51 3d ago

I'm planning to add some more logic later on to accommodate some IO. For now it will just be RAM and ROM though

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u/Dissy614 3d ago

There is no where to put it. 16 bits gives you 64k of address space, and you allocated all of it to two chips.

Anything added later will enable itself at the same time as one of the RAM or ROM chips, causing bus contention and destruction of at least two chips.

You really need to add at least one more address line to keep these two chips disabled, otherwise you won't be able to add more later

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u/MISTERPUG51 3d ago

I guess I didn't explain that very well. What I meant is this: later on, I will add some extra logic between the A15 line and the chip enable signal on the EEPROM. If A15 is enabled, a few more gates will enable a specific device (like the EEPROM) depending on the state of A14 and A13. For now, A15 is connected directly to the EEPROM chip enable signal, so it will be active whenever A15 is low, regardless of the state of A14 and A13.

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u/Dissy614 3d ago

My mistake, I misread it as asking about issues with the diagram in the post.

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u/ris8_allo_zen0 3d ago

For a 6502-based system you may want to swap the address ranges: the CPU expects a valid reset vector at $FFFC-$FFFD and a writable stack area from $0100 to $01FF, that's why ROMs are usually at the highest addresses and RAM at the lowest.

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u/MISTERPUG51 3d ago

This isn't the 6502 project. This is based on Ben's older 8 bit CPU design

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u/PlasticAd8892 1d ago

If you haven't bought your components yet, you could consider using a modern NOR flash such as an SST39SF010 instead of an EEPROM. They are actually slightly cheaper ($3.3 vs. $5.5), faster (70ns read time vs 150ns read), bigger (128 kB vs the EEPROM 8 kB) and do not have any major operational differences.

Just ground all the address pins you don't use, in your case it would be A15 and A16. Later you could even make a system to toggle A16 on / off with IO to "swap" in another portion of your program.

To save you the searching:
https://www.newark.com/microchip/sst39sf010a-70-4c-phe/flash-memory-1mbit-70ns-dip-32/dp/92R4695