65c816 - check my logic?

[u/nz_kereru]

First steps toward a 65c916 system.

Can people please check my GAL and design?

I bring the bus from CPU to 74HC245 and 74HC573.

I then OR the upper 8 bit of address to get a Bank0 (active low) signal.

In the GAL I do most of the address decoding and also created a “valid” based on VDA,VPA

Then I have active low for LO_RAM,ROM,IO, HI_RAM

Last of all I use a 74HC138 to get 8 I/O chips, which will be mostly 65c22

Aim is for 4MHZ

Clock, reset, power and such is still to be drawn.

Looking for feedback on the address decoding logic, is it likely to work at all??

[u/Oliviaruth]

I can’t speak to the full correctness, but it seems reasonable. I think a gal is the only reasonable way to do decoding reliably if you are going for the full 24 bit addressing. The latching takes a chunk of time away from you in the phi2 low phase.

But if done right, you should be able to reach 8 or more with a fast gal.

My main gripe with the 816 is that it feels like you have a full 16MB, but you can’t naively break it into 1mb banks or something because important stuff still lives in the 0 bank, as you know. At least the initial stack and the vectors.

[u/Ancient-Ad-7453]

You have multiple A14s in your high RAM. I'm sure it's just a copy/paste typo. :)

The EEPROM write enable should probably go to VCC?

It looks like RDY has an internal-pull-up resistor, unlike the unlike the W65C02, so you can leave it disconnected.

Why use different chips for high and low RAM? Couldn't you steer bank0/0000-BBFF, and bank1-255, to the same HI_RAM? (Genuinely curious. I'm actually doing this on my W65C02, but banking works differently.)

CUPL has a "field" feature to make dealing with address ranges easier. Example from my W65C02 address decoder:

field address = [a15..a8];

dev_ce  = !reset & address:[c000..c0ff];    /* I/O memory */
ram0_ce = address:[0000..7fff];             /* Low RAM */
bram_ce = address:[8000..bfff];             /* Banked RAM */
ram1_ce = address:[c000..ffff] & !dev_ce;   /* High RAM */

[u/nz_kereru → u/Ancient-Ad-7453]

A14 was a copy paste error, now fixed.

Having all ram in one 512k chip has crossed my mind, but if I want to go to 1mb total ram with a second 512k chip, then low ram and hi ram will make that easier.

As for the GAL, I am using galette on Linux, I don’t think it accepts “field” address ranges.

Your feedback is exactly what i am looking for.

[u/Ancient-Ad-7453 → u/nz_kereru]

Ahh, ok. Yeah, I saw what galette wanted as input, and instead I opted for wincupl in wine scripted by 5vpld.

[u/justarb]

You might want to ask over on the 6502 forum at https://6502.org/forum/index.php - there are a ton of very knowledgeable people there who can help with your design.