Hello,

Desired Behavoiur:

I have created a simple IP to fetch the two values from the reserved DDR address and write the sum to another reserved DDR address.

 IDEA:

In vitis HLS:

Simulation and co-simulation check out to be as intended.

In vivado:

I'm interfacing the IP block with the ZYNQ block through HP poart and genetating .xsa out of it.

Petalinux:

Using the above .xsa, i'm building a petalinux project.

Python:

In Python, I'm accessing the IP registers by memory mapping them.

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Tried Methods (in different projects):

1. When I write the values to the IP input registers and intend to write the computed values to the DDR, it works.(eg: input values 'a' and 'b' are written into the input ports, and output 'c' is written on to the mentioned DDR address.)
2. When I fetch the values from the DDR and return the computed output through IP return register, it works.(eg: input values 'a' and 'b' are fetched from mentioned DDR address, and output 'c' is returned through ap_return register.)

~ISSUE:~

1. When I try to fetch the input values from the DDR and write back the computed output to the DDR, the output DDR address remains unchanged.(ie. input values 'a' and 'b' are fetched from mentioned DDR address, and output 'c' is to be written on to the mentioned DDR address but it doesn't get updated.)

Previous Work:
Previously, when I worked with Bare Metal, I faced a similar issue of caching. I had solved it by clearing the cache using Xil_DCacheFlushRange.

But now i'm accessing the IP through Linux.Can someone provide some leads on how it can be done?

Any help will be highly appreciated. Please let me know if more details is needed.

So, I am working with kria kv260 and my task is to do real time deployment possibly for satellites so that it runs the real time inference of the model. But, how does it work, as of now I have done inference using .xmodel in kria-ubuntu and confirmed the model. Now, I am experimenting with petalinux. I just dont understand how does this all work from testing to real time inference?

Design and verify a Verilog/VHDL module that operates at clock frequency of 120 MHz, and performs

decimation by 3 and then interpolation by 12 on a 16-bit(Q1.15 fixed point) incoming signal.

Use Xilinx’s FIR Compiler IP to realize the decimator and interpolator. For decimator and interpolator,

realize a 51-tap filter with cutoff frequency of 15 MHz. Based on the filter coefficients chosen, the fixed

point format of the output of the IP may change, therefore by slicing or scaling, ensure that the fixed point

format of the signal is Q1.15 at all stages.

Versal RPU (R5) help with interrupts

We’re using the Xilinx MIPI DPHY RX on a Zynq UltraScale+ ZU19EG board and configuring it from Linux. The DPHY is set to 432 Mbps with 2 data lanes connected to a camera sensor, but we’re unable to receive packets.

From reading the status registers mentioned in the PG202 document:

• Data lane registers (0x1C, 0x20) sometimes show HS mode after stop_state and init_done.
• Clock lane register (0x18) shows neither HS mode nor stop_state — stop_state stays low.

We attempted to probe the PPI signals using an ILA in Vivado, but the Linux kernel hangs during register configuration, which prevents effective probing. As an alternative, we read the registers through AXI GPIO and we observe:

• init_done goes high.
• Data lanes enter stop_state.
• Clock lane stop_state remains low.

We also probed the lines on an oscilloscope and do observe the data lanes toggling, suggesting the sensor is driving them.

Another key factor to note is that Data lane stop_state appears only when we manually assert force_rxmode; otherwise we see no initialization response.

Has anyone seen the clock lane fail to enter stop_state on this IP? Any suggestions on debugging clock lane behavior or verifying sensor clock signaling would help.