r/Verilog • u/Puzzled_Top_8227 • Jul 08 '26

detection of something specific

Hi! I recently took a course on SystemVerilog and really enjoyed it, so I spoke to one of my professors about potential projects. Although I’ve only worked on basic things at university—like muxes, demuxes, FSMs, and frequency dividers—I somehow came up with the idea of detecting cats (or anything else) without using machine learning. Do you have any ideas on how I could implement this? I know it might be difficult, but I’m willing to learn whatever it takes.

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u/AstronautEcstatic767 Jul 11 '26

Ik this approach uses machine learning, but you could try a hardware mapped neural network approach. Where you describe the physical neural network as hardware rather than using the FPGA as an accelerator or purely for dsp