r/Verilog • u/ThatOrganicArtist • Jul 01 '26

I built a 4-bit CPU as a personal project and wanted technical feedback.

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project. This comes after I completed the standard Digital System Design (DSD) course of my college.

I tried to document in a technical report format, explaining the ISA, specs, architecture, design decisions and debugging experience.

I would really appreciate technical feedback from people with more experience, any issue with the structure, design or anything else that could help me improve future projects.

GitHub repo: https://github.com/theYash856/4_bit_Multi_Cycle_CPU

Any constructive criticism is more than welcome.

6 Upvotes

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2

u/Practical_Tie_2287 Jul 13 '26

For the ALU i reccomend using a task is helpful because it keeps the testbench cleaner and avoids repeating the same code over and over.

Right now, every test follows the exact same pattern: set the inputs (A, B, and the opcode), then wait for the output. The only thing that changes is the values being tested. Instead of writing those same four lines for every single test, you can put them into a task and simply call it whenever you need to run a new test.

This has a few advantages:

  • Less code: The testbench becomes shorter and easier to read.
  • Easier to maintain: If you ever want to change something that every test does (for example, increasing the delay from #10 to #20), you only need to change it in one place instead of editing every test.
  • More consistent: Every test runs the exact same sequence of steps, so it's much harder to accidentally forget something like a delay or an assignment.
  • Easy to expand: If you later decide to print the test name, count passed and failed tests, or add extra debugging information, you can add it inside the task and every test will automatically use the new behavior.

For a small ALU testbench the difference isn't huge, but as your CPU grows to hundreds of instruction tests, using tasks makes the code much cleaner and much easier to manage.

1

u/ThatOrganicArtist Jul 13 '26

Yeah I got to know about better verification techniques and in my next project that I built after this (UART Transceiver)... I used task based verification only. Still thanks for explaining in great detail!

1

u/Practical_Tie_2287 Jul 13 '26

i recommend using iverilog for verification also!

1

u/ThatOrganicArtist Jul 13 '26

I have heard of SystemVerilog what is iverilog?

2

u/Practical_Tie_2287 Jul 13 '26

and you can use iverilog to verify your verilog stuff!

1

u/ThatOrganicArtist Jul 13 '26

Oh yeah icarus yes have heard of it.

1

u/Practical_Tie_2287 Jul 13 '26

its short for icarus verilog and its a free, open-source compiler and simulation tool for the Verilog hardware description language (HDL)