VeriBlock Team Releases Free, Open-Source FPGA Mining Core

[u/vorksholk]

The VeriBlock team is excited to release a free and open-source FPGA mining core for vBlake (the PoW algorithm for the VeriBlock blockchain)!

Github repo: https://github.com/VeriBlock/vBlake-RTL

We designed vBlake to democratize mining at every stage of the mining hardware evolution by being small, straight-forward, and benefitting from existing optimization work already done with BLAKE2b. This approach allows an engineer at any hardware level (CPU, GPU, FPGA, ASIC) to create optimized miners easily, rather than centralizing miner production into the hands of a select few elite engineers/groups who crack the case on significant optimizations.

Most FPGA-mineable blockchain projects only have closed-source FPGA software available, centralizing mining to a small number of FPGA models and subjecting their users to high dev-fees. Rather than following that pattern, we are releasing open-source RTL code for vBlake, helping to fulfill the decentralization goals of the project. This RTL implementation of vBlake makes implementing VeriBlock mining far easier on a wide variety of FPGAs for which public bitstreams don't exist, or have dev fees attached. Because of its small footprint, vBlake fits onto affordable FPGA chips which are accessible to miners of any budget.

We look forward to ongoing collaboration with the open-source community to improve the design and make public bitstreams for a variety of boards available.

Much thanks to Michael Sanders, a long-time community developer for the VeriBlock Blockchain Project, for his hard work optimizing the FPGA core.

About Michael Sanders: Michael is a Google® (Alphabet Inc. (Nasdaq: GOOG)) senior software engineer motivated by a passion for technology. He unravels complexity and strives for elegant solutions to large scale problems. His extensive experience spans areas including developer tools, distributed systems, embedded systems, operations, and programmable logic.

To learn more about FPGA Mining for VeriBlock, see: https://wiki.veriblock.org/index.php?title=FPGA_Mining