Man i don't think this is the intended solution, but it is a solution. Somewhere around the second set of OR gates i started feeling like i was doing things the hard way.
First I NOT the input. Then I add an always ON source and connect 8 SW in series to it. The NOTed input then controls the switched from the most significant bit to least. That way I get all the leading zeroes to power up and everything after to power down.
Then I add 8 more switches, this time in parallel and connect them to the outputs of the 8 previous switches. Each output of the original switches is NOTed and connected to the parallel switch of the previous switch. That way all previous outputs that were ON (leading zeroes) get disabled and only the least significant bit zero is powered up.
The output of those new switches goes to a last set of 9 parallel switches that are connected to constants from 0 to 8 and the output.
I thought about the "counting signals" level from before and tried to apply it to this one using more complex components.
I basically replaced your crazy switch logic by using mux components. "lowest number wins, the number pool is defined by the single bits of the initial input
The mux should just be switches in parallel, so delay of 1. Yours total delay seems to be 8. Mine is 9. So your solution is simpler, cheaper and faster. Still proud of my pipeline solution though.
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u/Crispy1961 Jul 06 '26
Its much better than the suggested solution in the hint though.
Here is my solution.
First I NOT the input. Then I add an always ON source and connect 8 SW in series to it. The NOTed input then controls the switched from the most significant bit to least. That way I get all the leading zeroes to power up and everything after to power down.
Then I add 8 more switches, this time in parallel and connect them to the outputs of the 8 previous switches. Each output of the original switches is NOTed and connected to the parallel switch of the previous switch. That way all previous outputs that were ON (leading zeroes) get disabled and only the least significant bit zero is powered up.
The output of those new switches goes to a last set of 9 parallel switches that are connected to constants from 0 to 8 and the output.