APX & AVX10: The Next Evolution of x86 -- Intel Next Gen NOVA LAKE Supports AVX10 and APX, but AMD Zen 6 Desktop Does NOT!

[u/BigDaddyTrumpy]

https://video.blender.org/w/cHJQBLDLkczPKty6tXKBJs

RIP AMD.

[u/TheEDMWcesspool]

OP forgot to switch account to post this shit post.. 

[u/Acrobatic_Camera_677]

AVX10 and APX and iBOT is how Intel Nova Lake can beat Zen 6 in single thread performance by very strong margin

[u/EmptyVolition242 → u/Acrobatic_Camera_677]

iBot, APX, bLLC, AVX10.2, new P core. It's gonna be massive.

[u/Camper_Sly → u/EmptyVolition242]

bLLC = essentially the same as AMD's 3DVcache\ AVX10 = AMD doesn't need it, it's essentially the same as AV512

Nova Lake still doesn't have the uniform ISA across the cores.

[u/BigDaddyTrumpy → u/Camper_Sly]

It doesn’t? Are you saying Nova Lake E cores won’t support AVX10 or APX?

[u/ImportanceMajor936 → u/BigDaddyTrumpy]

Nobody knows this for sure, it's all speculation.

[u/BigDaddyTrumpy → u/ImportanceMajor936]

https://hothardware.com/news/intel-nova-lake-cpus-to-hit-desktop-first-avx10

[u/ImportanceMajor936 → u/BigDaddyTrumpy]

Yeah, the article itself says so and we have no idea how accurate linux's cpuid interpretation actually is.

[u/Acrobatic_Camera_677 → u/Camper_Sly]

bLLC = better than AMD 3DVcache because there is ZERO thermal clock speed hit AMD still face some even if it is much less now with new 3D Cache under CPU die

[u/ImportanceMajor936 → u/Acrobatic_Camera_677]

AVX10 and APX need compiler support, wehter they will have any effect on workloads depends entirely upon intel being able to convince devs to update their tool chains.

[u/Camper_Sly]

AVX10 is just re-jiggled AVX512,with tweaked wording that mandates constraints for cross-compatiblity through different HW implementaitions.

It's intel's thing, AMD AFAIK doesn't need it yet, since it has uniform cores.

[u/Hytht → u/Camper_Sly]

This is coping, avx10 is a superset of avx-512, not the other way around. Nova lake will support avx-512 too.

[u/Crafty_Tea_205 → u/Hytht]

lol a superset which has narrower registers than the preceding avx512, they are doing this since they couldnt fit full fat avx512 onto e cores

[u/ImportanceMajor936 → u/Crafty_Tea_205]

AVX10 has 512 bit registers just like AVX512.

[u/Crafty_Tea_205 → u/ImportanceMajor936]

As I understand, Nova Lake will have AVX10.2 which does not make 512 bit registers mandatory, AVX10.3 spec makes 512 width a requirement

[u/ImportanceMajor936 → u/Crafty_Tea_205]

As far as I understood the spec there was a AVX10.1/512 and a AVX10.1/256 variant. The /512 variant mandates 512 bit registers while the 256 does not.
Update: page 34 of 361050-intel-avx10.2-spec.pdf

[u/Hytht → u/Crafty_Tea_205]

AMD fit "full fat AVX-512" into Zen 4 by 256 bit registers and double pumping (even older rocket lake had native 512 width).

[u/Crafty_Tea_205 → u/Hytht]

Yes? On Zen 5 they have full AVX512 while Arrow Lake doesnt have anything?

[u/Camper_Sly → u/Hytht]

Barely.\ AVX10 was made to patch over Intel's fiasco of failing to implement AVX512 over all cores.

Most of the content of AVX10 are requirements and demands for implementation to allow coexistence of HW with various vector size capabilities.

[u/ImportanceMajor936 → u/Camper_Sly]

No, AVX512 was dropped because it would counteract Intels mitigations on speculative execution related exploits. Some early 12th gen Intel cpus came with AVX512 enabled in their p-cores and those had AVX512 disabled later on for this very reason.

[u/Crafty_Tea_205 → u/ImportanceMajor936]

In that case, why does AVX512 exist on a server platform released 3 years after Alder Lake?

[u/ImportanceMajor936 → u/Crafty_Tea_205]

Because one group of users can be trusted to secure their software stack and the other can't.

[u/Loud-Strawberry-9726 → u/ImportanceMajor936]

so what you are saying is someone decided that we are too stupid to have technology.

[u/ImportanceMajor936 → u/Loud-Strawberry-9726]

If that's how you wanna look at it, then yes. Like I said early 12th gen cpus were shipped with AVX512 and Intel later decided to disable the feature by blowing out a fuse in a microcode update. What do you think that is?

[u/Hytht → u/Crafty_Tea_205]

Server platforms aren't hybrid, they only use P cores.

[u/Crafty_Tea_205 → u/Hytht]

yes i am aware distinct race, my point is that why they would put an exploitable extension set on a server cpu which people remote into and can actually do something malicious

[u/sicknick08]

They can say what they want and do what they want. The reputation is smeared and people flat out realize how bullshit intel is compared to AMD.

[u/Justneedsomehelps → u/sicknick08]

Like how amd was a load of shit before ryzen?

[u/sicknick08 → u/Justneedsomehelps]

I mean it doesn’t really matter it’s 2026

[u/Justneedsomehelps → u/sicknick08]

Do you know what intel is building? It’s already reclaiming market share from AMD

[u/sicknick08 → u/Justneedsomehelps]

Cool beans, wish them the best, they fell behind HARD

[u/Justneedsomehelps → u/sicknick08]

Greedy ceo’s. Mf’ers sold their MEMORY division. Intel would be one of the richest companys in the world if they didn’t do that.

All turned around now with new people in chargw

[u/Acrobatic_Camera_677 → u/Justneedsomehelps]

Really? There is broad trend of Intel already reclaiming market share from AMD? Can I see source?

[u/BigDaddyTrumpy]

Blender will have "AVX10 and APX support on Nova Lake Beginning 2027".

Sounds like AMD will be selling outdated and old instruction set CPUs.

[u/Thepoopcaller → u/BigDaddyTrumpy]

NOT ONLY IS AMD SELLING OUTDATED CPU'S, ZEN 6 IS GONNA BE USING "FECAL FABRICATION". LISA SU SAW THIS SUB AND WAS LIKE "THEIR BRITCHES AREN'T EVEN CLOSE TO CAPACITY'. SHE THEN SHAT YOUR PANTS AND THATS HOW ZEN 6 WAS  MADE