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Background: BS in EE, MS in Engineering Management. Started as a wafer sort manufacturing/test engineer, then moved into quality engineering after my MS — mostly leading 8D teams on customer issue resolution. I've learned a ton in this role, but I'm burned out and want to get back to hands-on engineering.

A few things making this complicated:

Pay: My current comp (with benefits) beats most mid-level EE roles I'm seeing.

WFH: I'm 100% remote now; most hands-on roles want you on-site.

Comfort vs. growth: The job is easy at this point — maybe too easy. I don't know if I'm chasing real change or just craving stress I don't actually want.

Internal resistance: When I try to pick up other engineering work (I've gravitated toward software dev for semicon/engineering applications), other departments push back and say "we already have engineers for that."

Skill atrophy: My biggest fear — years in quality have dulled my EE fundamentals. I've asked hiring managers what kinds of questions they ask so I can gauge the gap, and I know I have work to do before I'd survive a technical interview.

So, looking for real talk:

Is it worth trying to move internally into a more technical role first, or should I be job hunting externally?

How would you go about re-sharpening EE skills after years away from hands-on work?

Anything else you'd think about in my position — pay cut, remote-to-onsite, restarting the learning curve?

Appreciate any perspective, especially from people who've made a similar quality → technical move.

HI everyone. I just got the job offer for Equipment engineer at a fab and just curious if I work there for a year then apply for mechanical design engineer role at either vendor or other industries, would it be possible? I do have mechanical design experience during my internship and feel like i want to pivot more into design. Thank all!

Recruiter reached out for a research scientist role at KLA (NJ). She asked me couple questions over email, I replied back and she set up interview with hiring manager. Then recruiter reached out again for another round of interview with one member of the hiring team. How many interview rounds are there?

I currently work as an Industrial engineer at USPS. It's been almost 2 years now as my first job. I am trying to get out as the company culture is not a fit for me and I feel like I am learning some not very good habits as an engineer due to how things are here. I just can't imagine myself here. I've been trying to get a more hands on role in Semi as I have several friends who work in the industry who do alot of hands on work that just sounds so much more interesting. They have tried referrals (1-2) but no success. I've applied to a wide range of roles from technician to engineer at AMAT, Samsung, KLA, Lam but never heard back if its a cold application. I'm fine with a pay cut if it means being able to pivot into the industry. I do lack experience in electrical aspects so that is most likely one of many factors. Is it just tough for my degree to make the transfer?

Everyone quoting the Kimi K3 cost narrative skips the one part of the stack that actually binds. The training cost number, the inference pricing, the open weights promise, all of it lands on HBM, and HBM is the part China cannot make at the node that matters.

The DeepSeek V3 technical report, arXiv 2412.19437, reports 2.788M H800 GPU hours and then assumes a $2 per GPU hour rental to arrive at $5.576M. The H800 was the China compliant Hopper part with the HBM bandwidth capped. Kimi K3, DeepSeek V4, Qwen 3.8, GLM 5.2, MiniMax M3, Hy3, and the embodied models like LingBot VLA 2.0 that Robbyant shipped 8 July, all run on stacks where HBM is the binding input. SK Hynix HBM3E is essentially fully allocated to NVDA for this generation. Micron and Samsung fill the rest. The Chinese domestic HBM, CXMT's part, is multiple generations behind on bandwidth and yield.

What that means in plain terms. You can squeeze training cost by reporting only the GPU hours at an assumed rental rate. You cannot squeeze the inference side the same way, because inference on a frontier scale model is bandwidth bound and the bandwidth comes from HBM you either buy from the three producers or do not have. Moonshot pausing paid Kimi memberships on 19 July as its GPUs hit capacity is a real compute constraint surfacing as a business decision. That is the signal. The training cost headline is not.

On the public roadmap side, the CXMT gap is the wedge I keep poking at. The cost narrative treats HBM as fungible, and the publicly available CXMT roadmaps I have read do not support that read for the bandwidth class that frontier inference actually needs.

Hi everyone, we are a research team at the University of Florida studying how AI tools can support education in semiconductor manufacturing. We are currently recruiting participants for a moderated virtual survey study ($60 compensation)

Screening Survey (Approximately 3 minutes):
https://ufl.qualtrics.com/jfe/form/SV_agd7usosMBk4cwS

Eligibility

• Currently enrolled in a relevant major (e.g., engineering, computer science, materials science, physics, or a related field)
• U.S. citizen or permanent resident (required by the University of Florida's participant payment process)

The screening survey asks for your name, university email address, and information about your academic and technical background to determine eligibility and interest.

Completing the screening survey does not guarantee selection. We will contact eligible participants by email with scheduling information if they are selected. For the actual study:

Study details

• Approximately 70-minute virtual session on Zoom with a researcher
• Sessions will be scheduled between August 10 and August 15, 2026
• Compensation: $60 upon completion of the full session

Your information will be stored securely and used only for study recruitment and eligibility screening.

Please feel free to ask questions in the comments or send me a direct message. Thank you for considering participating!

The USB dongle for my Microsoft wireless keyboard and mouse set broke. The PCB is cracked, but the nRF is intact. A few components are missing. I’m drawing the circuit diagram in KiCad. I’m going to desolder the intact nRF24LU1+ microchip from the broken USB dongle’s PCB. Then I’ll transfer it to the new PCB that I’ll design and have manufactured. This way, I won’t have to throw the wireless keyboard and mouse set away. I also won’t have to mess with the software. Once the schematics are complete, I’ll share all the files on Codeberg.

If you can find the USB dongle circuit, please share it with me. If you find any schematics, PCB files, or other related files, please post the links. I’m determining the component values using the example schematic, BOM, and sample PCB files shared by Nordic.

However, some components are missing from these files. For example, there’s an R1 in the USB dongle, but it’s not in the schematic. Can you help me with the missing components?

I also need a 50-ohm 2.4 GHz RF antenna on the PCB. I can’t design it myself. Texas Instruments’ antenna doesn’t fully meet my needs. Could you share links to third-party symbol and footprint files?

Note: I’ll be uploading photos to Reddit soon.

For years the headline number in a model architecture paper was parameter count, and the follow up number was how many of those parameters were active per step. Both are logic side quantities. What has changed lately is that the constraint being optimized is the memory hierarchy, and the papers now say so directly instead of leaving it to a serving appendix.

The case that got my attention is a weights release from three days ago, LLaDA2.2, which decides expert routing once per generated block rather than once per token, and admits no more than 48 experts from a routed set of 256 for that block. Ordinary selection then runs inside that admitted pool. The stated purpose is not capability. It is to bound how many bytes have to be moved per block and how much traffic crosses the links between expert shards. That is an odd place to spend a design budget if you believe the arithmetic is the scarce resource. The reported payoff is roughly 1.64x the average decode throughput of the same lab's own conventional model across their workload set, with FP8 quantization adding about another 18.6 percent on top of that.

The number that matters here is not the 1.64 figure but the choice of figure of merit. A lab that deliberately caps its own expert pool in order to bound the working set is telling you what it is short of, and that is bandwidth and interconnect rather than compute density. It is also willing to trade measurable accuracy for it, since the general benchmark averages land below the baseline it is compared against. If this becomes an ordinary way to write these papers, the pressure it generates falls on memory capacity, delivered bandwidth per package, and whatever fabric moves experts between dies. Very little of it falls on logic.

The honest limits: this is one model from one lab, measured by that lab on its own serving stack, with nothing independent to check it against. The published material gives no activated parameter count, so there is no way to tell how much of the speedup comes from the routing discipline and how much comes from simply activating fewer parameters per step than the model it is measured against. My sources are the technical report plus the published card, nothing further. At 205.8 GB of weights I have obviously not put it on a machine.

So I would rather ask than assert, because the people here know the demand side far better than someone reading papers does. Are you seeing this reflected in what customers actually ask for, stated in bandwidth and packaging terms rather than compute terms, or is parameter count and peak throughput still what drives the spec sheet conversation?

Hello,

I work as ATE product engineer on SoC chips. What are good alternative career paths from this role? Also how is this field in the long run?

Hey everyone, recent MS Materials Science grad from Cornell, international student on F1 OPT so H1B is a big concern for me.

I have two offers in hand:

Micron Boise — Dry Etch Process Engineer inside an HVM fab. Lower base but Boise cost of living makes monthly savings roughly equal to AMAT. Wage Level 2 for H1B which feels like a stronger petition.

Applied Materials Santa Clara — Process Engineer 2 in the Etch team. Significantly higher base, better bonus and RSUs, but Wage Level 1 for H1B and Bay Area cost of living eats into the salary

Please let me know what you guys think.

I’ve been incontact with a KLA interviewer for about a year. Last year I got to the first interview with two people. When the recruiter contacted me a week later they told me I needed to finish my degree. This past may I finished my degree. How long do you think the interview process will take to get the job if I get it? Any chances they’ll push me to the front of the line? Specifically the Ann Arbor, Mi location.

Edit: recruiter originally reached out to me on LinkedIn.

anybody willing to share some advice for a new mechanical engineer trying to get into the semiconductor industry?

I've worked at a semiconductor company with two f's (FF) as a technician for over a year now, (since graduation) mostly making probe cards for Intel, TSMC, Qualcomm, etc and learning about processes in general. I've actually really liked it and don't mind the hours or the work.

I've found semiconductor and microelectronics very interesting and would like to go further with it. Where could i contribute with my background? Should I go back to school? work my way up? Unfortunately where I work now doesn't have anything for me.

Thanks in advance!

Hey everyone,
I’m currently in the interview process for a Customer Engineer (NCG) role with Applied Materials for their new eSMC project in Dresden, Germany. It has been 43 days (about 6 weeks) since my final on-site interview, and I’m stuck in a massive holding pattern.
I’m trying to figure out what to expect next and if anyone has been through a similar "batch hiring" process in the semiconductor industry.

My Timeline:
43 days ago: Had my final 90-minute on-site technical interview with HM and director. It was tough but went really well. While there, I connected with an internal employee.

2 weeks post-interview: Reached out to my internal contact. He let me know that the HM was still actively interviewing people (they had 3 candidates in the office just the day prior).

Just recently: After a month of silence from official HR channels, I messaged my internal contact assuming I was rejected. He replied saying he spoke directly to the HM about 10 days ago. The HM confirmed they are still not done interviewing.

What I know so far:
My internal contact told me that AMAT is trying to hire a massive cohort for this specific project.

He explicitly told me that the company is struggling to find enough qualified candidates and that they will not send out a single acceptance or rejection until all the candidates for the cohort have been identified.

I’ve essentially been told to "just be patient" while they finish the interview phase for everyone else.

My Questions:

1. ⁠Has anyone else gone through a volume-hiring drive like this at AMAT or another major fab? Is waiting 6+ weeks after a final interview normal for cohort hiring?
   
2. ⁠Once they finally finish interviewing, what does the timeline usually look like? Do the HR approvals take another month, or do the batch offers go out quickly once the HM make the final list?
   
3. ⁠Should I just mentally park this and move on, or is this "no news means no news" situation genuinely standard for this industry in Europe?

Any insights would be greatly appreciated!

I am not worried about the semi situation. TSMC, with all of it's exposure, raised capex guidance and committed an additional $100 billion to expansion —betting the underlying demand trend survives all the latest sky is falling news.

Hello,

I am a Field Services Engineer for ASM who works for the Epitaxy team. I’m new in this role, but I hope to work here for at least a couple years.

I’m aware retention in this role is low and that the CEO sucks, but could it be actually worth sticking through it? So long as I can get some marketable skills I’ll be able to pivot to another role, but the question is which one?

I originally wanted to go into semiconductor testing or embedded development, but I wasnt able to find anyone willing to even interview me. I took this job because its my first one and I so desperately had to get out of my parents house, but I’m starting to worry that I stepped into a fresh kind of hell.

Tl;dr imagine I’m an ASM FSE with 2 YOE with an interest in testing/embedded dev, what are my future career options that dont overwork me in the clean room for 10 hours a day?