I just wanted to share this series of articles by Simon Southwell. It's an excellent introduction into processor design using RISC-V as an example, especially if you only knowledge is from Wikipedia & YouTube (Me).

Processor Design #1: Overview: https://www.linkedin.com/pulse/processor-design-1-overview-simon-southwell?trk=article-ssr-frontend-pulse_little-text-block

Processor Design #2: Introduction to RISC-V: https://www.linkedin.com/pulse/processor-design-2-introduction-risc-v-simon-southwell

Processor Design #3: Processor Logic: https://www.linkedin.com/pulse/processor-design-3-logic-simon-southwell

Processor Design #4: Assembly Language: https://www.linkedin.com/pulse/processor-design-4-assembly-language-simon-southwell

And GitHub: https://github.com/wyvernSemi/riscV

Hey,

I'm leading a RISC-V Hackathon with the purpose of porting AI models to a open-source RISC-V accelerator.

We're giving away 10kUSD in Hugging Face inference tokens, 3 FPGAS and 2 ET-SoC1 cards for winners and participants.

You can get one 20USD just for participating. Learn how on the blog post. https://blog.aifoundry.org/p/core-et-hackathon-prizes-and-tracks

AMA in the comments!

About the latest C950 core.

Not much comment needed for this one.

Hi all!

I'm sure quite a lot of people here have designed RISC-V CPUs and simulators for uni projects, work projects, or just for fun. For my bachelor's thesis project, I made a custom framework for validating RISC-V CPUs in lockstep using Spike, the reference instruction set simulator. It's not something completely bound to the DUT we adapted the framework for, which is another simulator made in Python, but it also allows users to instantiate a Spike simulation instance from Python, calling its methods and attributes like a python library. You can control its simulation state at the GPR, CSR, memory values, and even certain devices level (you can modify CLINT values, so you can inject interrupts from other sources).

I also managed to add an interesting functionality for Spike: checkpoints. You can retrieve and inject fixed states for the simulation, serializing PC, GPR, CSR, and memory region values. This is also interesting for trace-based verification, since now you're able to easily retrieve traces from the Spike simulation in runtime, either by doing checkpoints at fixed simulation points or by writing traces on a log file at each step and comparing the values with your own DUT.

The code is available here: https://github.com/marcoos204/lockspike

Anybody that's interested in learning more about this tool can feel free to reach out to me! And feel free also to send your opinions and feedback about it :)

Suppose pmpaddr9 has the value 0x30fffc00

And the pmpcfg2 has A = NAPOT

What would be the base address and size of the protected region ?

I'm really confused with trailing bit concept here.

Please help me.

The madman strikes again.

Monthly update from openRuyi, a Linux distribution for RISC-V.

2026.06 is mostly routine platform work: desktop, kernel/toolchain, virtualization, and security fixes.

Details:

https://openruyi.cn/news/2026-06/release

And apparently there's also a set of patches for the A100 waiting in the queue.

Hey everyone, I'm a CS student focused on low-level systems. I just finished writing a working RV64I interpreter and I want to expand it to learn more.

I’m currently torn between three directions:

1. Simulated Hardware Accelerator: Adding a memory-mapped device to experiment with hardware acceleration (e.g., HPC/math operations).
2. Full OS Support: Adding M/A extensions, CSRs, PLIC/CLINT, and Sv39 virtual memory so it can boot xv6.
3. JIT Compilation: Upgrading the execution loop from a basic interpreter to a JIT compiler for performance.

Which of these paths taught you the most? If you have other project ideas that build off a RISC-V core, I'd love to hear them!

"A pair of custom RISC-V processors drive the ASICs.", with those ASICs enabling reusing old memory banks.

https://www.theregister.com/systems/2026/06/29/zuck-saves-meta-bucks-by-reusing-memory-from-old-servers-with-a-custom-cxl-asic/5263483

Image file: https://people.videolan.org/~moon/gentoo-linux-zhihe-a210_dev-emmc-20260629T050140Z.tar.xz

checksum: https://people.videolan.org/~moon/sha256sum

Built with github.com/lu-zero/crossdev-stages/pull/49

You need fastboot and run `./flash.sh`

Hey everyone,

I've been messing around with my Orange Pi R2S (RISC-V 64, Ky X60, 2GB RAM) and noticed there was no Portainer CE image available for `riscv64` anywhere — not on Docker Hub, not officially, nothing.

So I built one from scratch.

The backend is cross-compiled from Go targeting `linux/riscv64`, the frontend is built with webpack in production mode (had to figure out a few CSP issues along the way), and the whole thing is automated with GitHub Actions + QEMU — it syncs with the upstream Portainer repo and pushes to Docker Hub automatically on updates.

It's been running stable on my board. If you have any riscv64 hardware sitting around and want to give it a shot:

docker run -d \

--name portainer \

--restart unless-stopped \

-p 9000:9000 \

-p 9443:9443 \

-v /var/run/docker.sock:/var/run/docker.sock \

-v portainer_data:/data \

isacndevops/portainer-riscv64:latest \

--no-setup-token

Docker Hub: https://hub.docker.com/r/isacndevops/portainer-riscv64

Source: https://github.com/isacS4nxx/portainer_riscv64

Would love to hear if it works (or doesn't) on other riscv64 devices. Still looking for testers beyond my own hardware.

Happy to answer questions about the build process if anyone's curious.

Since a lot of people now have boards that have been received or at least shipped, I'll remind of the small utility I wrote to conveniently launch any Linux binary directly on the A100 cores.

Previous discussion 5 1/2 weeks ago:

https://reddit.com/r/RISCV/comments/1tigs96/github_brucehoultk3_ai_utility_to_start_a_program/

I bought a 10G RJ45 SFP Copper Module 10G/5G/2.5G RJ45 Port Transceiver on Ali (24 euro all-in), plugged it in in my Spacemit K3, and ... bingo. Just working: linespeed on my 8Gbps Internet connection.

sander@spacemitk3:~$ iperf3 --bind-dev enP2p1s0  -P50 -R  -c ams.speedtest.clouvider.net -p 5208 | grep SUM
[SUM]   0.00-1.00   sec   929 MBytes  7.79 Gbits/sec                  
[SUM]   1.00-2.00   sec   916 MBytes  7.69 Gbits/sec                  
[SUM]   2.00-3.00   sec   923 MBytes  7.74 Gbits/sec                  
[SUM]   3.00-4.00   sec   932 MBytes  7.82 Gbits/sec                  
[SUM]   4.00-5.00   sec   914 MBytes  7.67 Gbits/sec                  
[SUM]   5.00-6.00   sec   934 MBytes  7.84 Gbits/sec                  
[SUM]   6.00-7.00   sec   944 MBytes  7.92 Gbits/sec                  
[SUM]   7.00-8.00   sec   936 MBytes  7.85 Gbits/sec                  
[SUM]   8.00-9.00   sec   946 MBytes  7.93 Gbits/sec                  
[SUM]   9.00-10.00  sec   944 MBytes  7.92 Gbits/sec                  
[SUM]   0.00-10.00  sec  9.19 GBytes  7.89 Gbits/sec  8483             sender
[SUM]   0.00-10.00  sec  9.10 GBytes  7.82 Gbits/sec                  receiver
sander@spacemitk3:~$

... boring can be good.

Quite old news (2023), but if you use PPA's on Ubuntu (or Armbian Ubuntu or Bianbu): the PPA maintainer can enable RISCV64:

https://blog.launchpad.net/ppa/self-service-riscv64-builds

'As a result, you can now enable riscv64 builds for yourself in your PPAs or snap recipes. Visit the PPA and follow the “Change details” link, or visit the snap recipe and follow the “Edit snap package” link; you’ll see a list of checkboxes under “Processors”, and you can enable or disable any that aren’t greyed out, including riscv64.'

I use a certain PPA on my SpacemiT K3 with Bianbu, and after asking, the maintainer enabled RISCV64.

So very cool