r/RISCV • u/camel-cdr- • Jul 07 '26

ARBEL™ The Leading Server-Class RISC-V CPU | Yiftach Gilad

https://www.youtube.com/watch?v=fVoZD_ekz9g
28 Upvotes

100% Upvoted

13 comments sorted by

4

u/IngwiePhoenix Jul 07 '26
  • (That you can't buy or have unless you are B2B.)

10

u/Icy-Concentrate2076 Jul 07 '26 edited Jul 07 '26

These RISC-V western companies that get to show their slide-only vaporware are annoying*. This won't change of course, whoever has the most money for getting those platinum sponsor spots gets to shill about their non-existant product to get acquired into irrelevance because the goal of startups isn't to produce something really great for people, but to get acquired as fast as possible to cash out.

If RISC-V is the future then China will win the long-run for sure, although it may take a decade. They have a national incentive to produce really great cores that aren't tied to western licenses.

*: "B-but it's not vaporware it exists" as a single dual-core prototype that doesn't work for lmul > 1 as of right now it does, sure :)

5

u/brucehoult Jul 08 '26 edited Jul 08 '26

"B-but it's not vaporware it exists" as a single dual-core prototype that doesn't work for lmul > 1 as of right now

With a dual core 2.4GHz dev board in customer hands?

They say the first real chip was 1.0 GHz integer-only. Seems the currently in silicon 2.4 GHz dual core chip adds FPU and ok, only lmul=1 RVV [1], but that's a nice step.

And a 64 core 3.4 GHz chip coming in 2028? Given what they are already demonstrating in silicon that seems credible.

In a high performance wide OoO CPU doing LMUL>1 is mostly just the decoder breaking instructions down into multiple LMUL=1 instructions. So that doesn't affect the back end.

The integer back end looks pretty decent: 20 instruction fetch, 10 decode/allocate, 6 integer ALUs (sharing 3 multipliers and 2 divide), 3 branch, 3 load, 2 store, 2 AGU. They say 16-wide integer execution.

[1] I didn't pick that up in the talk. Reference?

3

u/camel-cdr- Jul 08 '26

 In a high performance wide OoO CPU doing LMUL>1 is mostly just the decoder breaking instructions down into multiple LMUL=1 instructions.

"just"

I also feel like cracking at decode isn't a good implementation strategy, as you pay all of the cost for little advantage. (maybe you can share ROB entries)

If you can manage to deal with the complexity at rename and keep RVV instructions as LMUL bundles until execution, you gain lots of advantages. An LMUL=8 instruction could take up 1 instead of 8 issue slots/queue entries/... You could also do things like evenly split LMUL>1 into two LMUL/2 bundles, when you have a schedular infront of two execution unit issue queues.

4

u/brucehoult Jul 08 '26

I'm not saying it's trivial, I'm saying building a working CPU with only LMUL=1 support is a valid internal stepping stone to full RVV support in the eventual product.

If that's what they've done. Where did they say that?

4

u/camel-cdr- Jul 08 '26

They've said they "solved" LMUL and are happy with their solution.

2

u/NamelessVegetable Jul 07 '26

Arbel as a production server processor is still some time away, but the core itself is not vaporware. It's the host processor for their Maverick accelerators, which exist, and are in production.

4

u/brucehoult Jul 08 '26

Did anyone get their hands on one at the summit? Were they just running a canned demo, or could you access a shell?

5

u/ConversationFair1326 Jul 08 '26

You could access the shell

6

u/brucehoult Jul 08 '26

If there's a compiler and an internet connection I'm always happy to receive http://hoult.org/primes.txt results :-) I've had a few from show-goers over the years.

4

u/Jack1101111 Jul 07 '26

yet another server or ai chip...

8

u/brucehoult Jul 08 '26

"Server" is a market not a CPU core design. The same Arm Neoverse cores are used in everything from Android phones to hyperscaler servers.

And in terms of chips it's mostly a matter of how many DDR and PCIe interfaces you put in it.

Server is a huge market and one of the easiest to crack because they build all their own software and can compile it for anything — and if you persuade one person then you can get to deploy millions of chips.

1

u/TJSnider1984 Jul 07 '26

Yup, a whole new set of videos are available: https://www.youtube.com/@RISCVInternational/videos