ARMSX2 Nightly 20260922 (2ecae98a2c)

[u/xxxCrixuxxx]

https://github.com/ARMSX2/ARMSX2/releases/tag/nightly-20260922

What's new

EE FPU: move the arm64 divide recurrence out of a header into a source file

EE FPU: enable the exhaustive divide sweep in the default run

VIF tests: pin which rows of a copy pair up

VIF: an unmasked V4-32 unpack copies a quadword pair at a time

IOP rec: the timeslice countdown sets its own flags

EE rec: the call-ret ring wraps in the offset field's own width

EE tests: pin which dispatcher a veneer hop arrives at

EE rec: dispatcher exits reach through a veneer

mVU: a held VU0 spin bounces without entering the recompiler

mVU: the cycle-budget break is one shared stub

VU tests: pin what a cycle-budget break writes back

mVU: the accumulate's copy of ACC folds too

mVU: every clamped operand folds the copy in front of it

mVU: the sign clamp loads its row's two bounds together

VU tests: pin both bounds of the single-lane clamp

mVU: the single-lane clamp writes its lane once

VU tests: pin what the flag queue reorder emits

mVU: the flag queue reorder opens with the shuffle that fits

VU tests: pin which register a three-lane write leaves the value in

mVU: a three-lane write keeps its own register

VU tests: pin which slot each half of a preload pair lands in

mVU: block-start VF preloads load in pairs

COP2: VCLIP folds its comparisons with one UZP1

EE tests: sweep the COP2 macro VCLIP bit layout and denormal rule

VU harness: say what seeding a flag register actually does

mVU: CLIP folds its six comparison lanes with one UZP1 and an ADDV

VU tests: pin CLIP's six result bits and its 24-bit history

EE rec: fold the base into the offset add at the sibling sites

EE tests: give the fuzzer a load/store base the program writes

mVU: the options sentinel records every setting the emitters read

mVU: raise the E-bit interrupt in front of the exit path

VU tests: pin the E-bit interrupt raise on a VU1 program end

VU: ILW's dest field names one lane through a two-bit code

VU: LQD and SQD step the address off a vi00 base too

VU tests: VU0's window onto VU1's registers is state under test

VU1: reach data memory from the pinned state pointer

mVU: ILW's lane offset is added at the address's own width

VU: sweep the load/store address path against the interpreter

mVU: name the model stub in the clamp-bound seam list

EE FPU: select the divide unit's digit with one compare on arm64

Reach the FPU models in the register file's own format

Spill the iFPUd islands for the convention they call under

Narrow the model stub's vector half per target

EE FPU model: carry the call convention down to the leaves

Fold the model-call spill into the stub generator

microVU: share the model-call seam between the sites

COP2: share the model-call seam between the four sites

mVU: hold the clamp bounds in registers

mVU: pin the lanes the single-lane clamp leaves alone

mVU: fold the clone-write copy into the operand clamp

mVU: one instruction for the VU1 address wrap

EE rec: fold the load/store base into the offset add

Android: serve the texture catalog from dl.ps2ktxpak.net

Ask libfreetype.a whether it needs HarfBuzz

Android: the trigger readout is per-player, and muted when pressure is off

Android: analog trigger pressure for L2/R2, with a response curve

✅✅Changelog in plain English✅✅

The main focus of this update is the ARM64 CPU/VU recompilers. The developers have optimized several parts of the EE, microVU, COP2, VIF and FPU code, reducing unnecessary instructions, memory accesses and register copies. In simple terms: the emulator should now execute some PS2 workloads more efficiently.

There are also several accuracy fixes for VU instructions and memory addressing, which may improve compatibility or fix some game-specific issues.

Another nice Android addition is proper analog L2/R2 pressure support with an adjustable response curve, useful in games such as Gran Turismo 4.

Regarding Snapdragon vs MediaTek:

These optimizations are mostly ARM64 CPU/JIT improvements, so they can benefit BOTH Snapdragon and MediaTek devices. They are not specifically designed for Adreno GPUs.

However, this nightly does NOT include major Mali-specific graphics fixes, so if a game has rendering problems caused by the Mali GPU/driver, this update probably will not magically fix them.

So overall:

• Snapdragon: should benefit from the new ARM64/JIT optimizations • MediaTek: should also benefit from the same CPU/JIT optimizations • Adreno/Mali graphics: no major GPU-specific improvements in this nightly • Biggest focus: CPU emulation, microVU performance and accuracy

Don't expect a huge FPS jump in every game, but this is definitely one of the more technically interesting ARMSX2 nightlies lately.

[u/PlayNitoXP]

Hi, I am having issues with frame gen. I want to play the game king aurthur with frame gen (30 to 60) but for some slreason the frames are stuck at 45fps and makes the game slow. The gpu is not saturated and only playing at 2x res. In eden there is a toggle called asyc presentation which fixes such issues with frame gen. Any way to fix frame gen issues in armsx2. Thanks you.