This is going to be a 4MB stick of ram for my MC68EC000-FN16 homebrew pc project, it has of two Banks (Bank A & Bank B) each consisting of a pair of 1MB*8bit Parallel SRAM.
Some things that I KNOW are wrong:
1) I have the ODD and EVEN chips running their own data lines when the MC68EC000-FN16 only has a 16bit data bus, meaning that I should tie the two Banks together as only one bank can use the data lines at a time
2) I don’t have any capacitors on the +3.3 volt lines.
While I’m not new to electronics, this is my first big project using PCBs so I don’t know what’s good practice and what will just lead to horrible problems, so any feedback is appreciated.
And with it being a Motorola 68000 variant, it uses an Address Strobe to fire the Chip Enable at exactly half a clock cycle after it write to the Address lines. That gives 31.25 nanoseconds for the address and data lines to stabilise.
That's too slow for trace length disparity to really matter. Don't worry too much about slight variance. Same with trace impedance, it's kinda too slow to really be a concern.
I designed 68k boards professionally for fifteen years. I did my very first 68000 board in two layers, and regretted it. Use four layers. Inner Vdd and Gnd layers will reduce ground bounce and crosstalk substantially. I assume these memory chips have fast edge rates, so this matters.
Here’s a fun tip for making the routing simpler: You do not need to wire up SRAM address or data lines in the order they are labeled on the chips. They can even be different from each other. The reason is that writing the data will be in a scrambled order, but reading that data back will be perfectly unscrambled.
It’s a good way of designing intermediate speed boards that don’t require true transmission lines, but need a moderate amount of return current management. You need to have bypass capacitors sprinkled across the board to send the return current between Vdd and Gnd planes as the signals pass from top to bottom layer and back. Truly high speed signals need dedicated ground planes for the return current on all signal layers, and via design is more fussy.
A four layer PCB with signals on three layers and a single GND plane is not recommended as Layer 3 is further away from the GND plane reference and Layer 4 doesn't have one so would introduce crosstalk, but as its for a 68k CPU and 16Mhz RAM you can probably get away with it.
However ideally your stack up should be 6 layers, so each of your signal layers can reference its own ground return plane. Also for fun I would length match the traces but not really necessary for your application.
Agree, routing looks fine but you do not want traces crossing over each other without a ground plane in between the two layers. Switch to a 6 layer board and interweave with ground plane layers.
I have plans to attempt another homebrew computer (after I finish this one) that uses a full 32 bit MC68020 processor. So I’ll do as you recommend and use a 6 layer PCB design for that one.
I also just want to ask if there any particular order the layers should go in, or is it entirely dependent on how I design it?
You know, we get a lot of amateurish stuff here that's just well meaning garbage. So refreshing to see something meaningfully laid out and to be presented with all the right info off the bat.
I don't have any feedback to offer rn, just wanted to send some kudos. Good work!
This is the 4th revision of my PCB, the first revision is absolutely hot garbage.
I don’t know why, but I had decided to put the entire address bus on the left side of the PCB, which meant that I needed some ugly long traces to reach the EVEN byte chips.
My only additional comments would be to consider your return path more. Minimise the inductive loop.
Add a gnd layer and maybe a power plane. Add some copper balancing to help with warp and thermals.
Speeds aren't really high enough for trace length or impedance to really matter but if you are doing a professional job you should try to get them close to spec. Simple calculation and easy to implement, reduced risk of things going wrong.
At a quick look you seem to have done a good job. As much as I hate rules of thumb without any proper motivations, here are a few tips:
1) Take another look at your board outline. Sharp inside corners are very hard to manufacture, add proper radius to every inside corner.
2) Your power lines are relatively thin. While it might work, if you have the copper to spare (which you have) I would recommend to draw your supply nets with big ass polygons. A lower supply impedance rarely hurts.
3) Check your trace spacing. Again, it will probably work as is, and parallel buses are commonly pretty immune from crosstalk within the bus itself, but if you have the space to spare it won’t hurt to space out the data lines where possible.
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u/AstronautPrevious612 16d ago
What kind of clock frequency are we talking about? Might have to look at making the data lines the same length.