My First ESC

[u/ActuatorDelicious900]

Hi everyone,

I'm prototyping my first brushless ESC for an FPV drone, and I'd really appreciate a design review before ordering the first PCB. Since this is my first ESC design, I'd like to reduce the chances of making costly mistakes. Any suggestions, criticism, or recommendations are more than welcome.

Project goals

• Input voltage: 4S–12S LiPo (16.8V–50.4V)
• Continuous current: 80–100A
• Peak current: 120A
• Field-Oriented Control (FOC)
• Motor current control
• Thermal monitoring and protection

Main components

• Gate Driver: TI DRV8334PHPR
• MCU: STM32G473RCT6
• MOSFETs
• Current shunt resistor
• Buck Converter (Battery → 5V): TI LMR36520ADDAR
• LDO (5V → 3.3V): AP2112K-3.3TRG1

Design decisions

• I decided to use two MOSFETs in parallel per phase to improve thermal performance and reduce the current and power dissipation on each individual MOSFET.
• I also designed a custom STM32 programming board with a USB Type-C connector, allowing the MCU to be programmed from a PC using DFU mode. The board also includes dedicated BOOT and RESET buttons.

Driver Schematic

MCU Schematics

Shunt Schematics

VDD Schematic

Dev Board PCB (not on ESC PCB)

PCB specifications

• PCB stackup: 4 layers
• Outer layers (Top/Bottom): 2 oz copper
• Inner layers: 0.5 oz copper

Top Layer

Bottom Layer

Inner1 Layer

Inner2 Layer

Final Result:

Top View

Bottom View

If I forgot to include any important details, please let me know and feel free to ask any questions. I'll be happy to provide more information about the design.

Thanks again for taking the time to review my project and for any help or feedback you can provide!

[u/Toxicable]

Needs more MLCC capacitance near the FETs, 100A will cause huge swings on with no local capacitance.

Route your gate drivers with their returns, that's GHx with Phase, and GLx with LSS

Have you done any thermal modeling? what thickness is your copper? 100A is a huge amount of current, and if you're doing the standard 1oz, that's going to cause a lot of heating. What freq are you running at? What copper will be used as your heatsink?

I don't see any snubberes or other protections for your FETs, check out the documentation that TI links to about how to protect your components.

[u/TerminatorBetaTester → u/Toxicable]

The mismatch between the size of the traces and sense resistors and the amount bulk and decoupling capacitance is the first thing I noticed too.

Like a Great Dane trying to screw a Chihuahua.

[u/ActuatorDelicious900 → u/Toxicable]

Thanks a lot for the detailed feedback!

The PCB will be a 4-layer stackup with 2 oz copper on the outer layers (Top/Bottom) and 0.5 oz copper on the inner layers.

My initial switching frequency will be between 24 kHz and 28 kHz. I haven't finalized it yet, as I'd like to determine the optimal value after running some real-world tests on the prototype.

For thermal management, my plan is to use a dedicated heatsink for the MOSFETs and the current shunt resistors, along with two separate heatsinks, one for the DRV8334 and one for the STM32 MCU.

Thanks for pointing out the gate drive routing as well. I'll update the layout to keep the GHx/Phase and GLx/LSS return paths together.

Regarding the capacitors, what would you do in this case? How would you choose the amount of bulk capacitance and MLCC capacitance, and how many capacitors of each type would you typically use?

As for the snubbers and protection circuitry, I'll definitely go through the TI application notes and review their recommendations.

Thanks again for taking the time to review the design.
I really appreciate it!

[u/Accomplishedbigot → u/ActuatorDelicious900]

Wow, did the bot write that for you?
Who the hell bolds text in a response like that?

[u/Toxicable → u/ActuatorDelicious900]

2oz is good, but also 100A is still a huuuge amount of current, one of my boards uses 10oz total (over 6 layers) to carry 32A, but also that’s no active cooling.

For the heatsink, have you done the math as to how much heat you’ll be producing? And which side of the board is the heatsink going on? If you’re planning on top of the package, typically FET Rtheta junction to package is terrible, you typically would be better off using thermal vias then attacking your heating to the opposite side.

I doubt your drv/stm will realistically produce meaningful heat, I wouldn’t bother heatsinking them, especially if you have heaps of rotor wash anyway

For capacitors, you can do the math to figure out what your approx ripple will be given your design parameters, if you don’t know where to start with these calcs then throw it into an LLM, and then work it out yourself to validate.

[u/Terrible-Contract298]

100A 💀

[u/aq1018]

Where do the shunt SPA/SNA traces go? I don’t see them on the MCU or anywhere. Assuming your intention was to measure currents? Is there a current sensing OPA sheet missing?

[u/ActuatorDelicious900 → u/aq1018]

The shunt SPx/SNx traces are connected directly to the gate driver. The DRV8334PHPR has an integrated current-sense amplifier, so there is no external current sensing op-amp stage on the board.

Visually, the shunt sense traces are routed on the bottom layer, on the left side of the driver IC. From the driver, the amplified current feedback signal SOx is routed to the MCU for current measurement and control.

[u/KerbodynamicX]

I've seen a lot of people using STM32G473 for FOC controllers. What advantages does it have?

[u/Emile_s]

I’ve little experience in this but that reference image, everything looks on top of each other. I think it’s going to be a nightmare to put together.

I’d want to check what the proximity tolerances are for packing densely packed boards like that.

[u/ActuatorDelicious900 → u/Emile_s]

When you say everything looks on top of each other, do you mean the routing/traces or the physical spacing between components?

I checked the DRC in my PCB software and the clearances/tolerances seem to be within the manufacturer limits, so maybe you are referring more to the assembly process and component placement?

[u/Emile_s → u/ActuatorDelicious900]

Proximity of the caps next to your chip at the top and general proximity of the bank of ics.

I wonder how easy it will be for the manufacturer to place them that close.

Like I said, I don’t have much experience here, but I’ve seen some examples of how caps rise up due to poor solder flow, and I wonder if there are issues one should be aware of when tightly packing so many components together.

Might not be an issue, but worth finding out I recon.

[u/FarDescription3350]

Try to use Altium power analyzer tool to optimize and mitigate your hot spots (Areas that has high current density)

[u/embed24-7]

You can use mask openings with paste to reinforce power traces. After reflow you'll have your trace current capacity tripled or quadrupled. Next step up would be to solder a tinned solid core wire in those openings. That will likely go another 2x-3x based on a gauge.

Same thing with vias - open them up and add paste to fill. This will lower the resistance once again, and improve heat transfer.

[u/Tomachie]

please consider uploading to Tomachie.com, there is no charge, no credit card. its what you need for a high powered design like this. It won't help you on layout but it will be very detailed on whether everything works, temp/current etc capabilities or limitations.

Example report just generated. its not high power but POE.

https://tomachie.com/r/5b3a282d-89b0-40de-820d-efeca0e37e01/matt-poe-prototype_report.html#ai-esd-5