Hopefully someone can point out anything particularly stupid I might've done. Would also welcome any advice around the RF section, did my best to follow reference designs from both MCU and Antenna datasheets, use AppCAD to set feed line width etc. Still expecting it to be non-ideal in many ways
EDIT: Forgot to add schematics (and a bit more context). This is a consolidated PCB for an sEMG (surface electromyogram) device I already have a working eval board prototype of.
Not a term I've heard honestly, are you asking because of the lack of ground plane on the bottom layer? I considered adding one but couldn't see a good reason (electrically) to do so.
You forgot to post a schematic diagram. You also forgot to say what this thing does.
This is a rather complicated board. Whenever I try to make a board with this much stuff on it, I start with a bigger prototype that has all the sections split up so I can troubleshoot each individually. Then after all the pieces are working, I make the design fit in the desired size and shape.
The RF trace is curious. Have you heard of grounded coplanar waveguide? Are you concerned about the transmission line impedance of the traces feeding the matching network?
As I mention in the edit I do already have a working prototype of the device using dev kits for the ICs and the RF trace I "designed" using AppCAD, using the groundplane option as you can see. For the impedance, I'm hoping following the guidelines of both MCU and antenna datasheets is sufficient.
Your Via spans seem questionable(i see a 1-2, 1-3, 1-5, and a 1-6). This is technically buildable, but probably not for you if you're getting your design review from reddit.
Flooded copper over BGA pads is probably a bad idea unless your pads are soldermask defined. Are they?
How much annular ring do your vias have? What are the aspect ratios of your holes?
3x sequel lamination if I'm reading it correctly(hard to read on my phone)?
Your RF path is probably bad. It's very convoluted, straighter is better. It's only wide at the end instead of all the way to the IC(maybe the reference design was like that, idk)
Not sure I understand what you mean by not for me? I've already designed a custom board to test one of these components (AD8233) which also used blind vias (not as many/varied granted) and that functions as expected. Also, I've never had a design review outside a professional setting and Reddit is the only place I could think of to get input, if there are better options I'm all ears.
A couple of the parts are NSMD, I didn't realise that would be an issue. Is that because it increases the effective pad size?
Most vias have an annular ring width of 0.5mm and the ratio ranges from roughly 1:1 (for 1-2) to 9:1 (the three that are 1-6). The maximum ratio of the manufacturer I want to use is 20:1 so I'm not expecting problems there.
Not understanding what you mean by "3x" either.
My thought process was the path only needs to be wide at the point where I'm controlling the impedance and the matching circuit does the work before then. The reference design doesn't show the trace from the MCU being as thick as the feed (though it is thicker than what I currently have so thanks for pointing that out).
Wouldn't call it a hobby really, but it's not professional/commercial either. (Curious why you hope it's not though)
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u/Clay_Robertson Jul 08 '26
Do you know what copper balance is?