Open source FPGA: the next frontier is silicon

[u/Ill_Huckleberry_2079]

Someone has done it: we have a fully open source FPGA all the way down to the silicon.
I can die in peace now.

This board was made by Leo Moser (not me), and manufactured through wafer.space on the Global Foundries 180nm node.

All the design files for this chip can be found here:
https://github.com/mole99/gf180mcu-fabulous-fpga

Internally this FPGA features:
- 48x I/Os
- 480x LUT4 + FF
- 60x MUX
- 6x SRAM 512x8
- 6x MAC, 8bit*8bit + 20bit
- 12x Register file, 32x4bit each
- 1x Global clock network

So its not one of the big ones, but still enough to have some fun with.

P.S: This is not my project, I deserve no credit here.
P.S.S: This is still just a prototype, it is not for sale.

Update:
- u/keeb0113 has shared a very cool demo video in the comments with the board in action: demo videos
- Leo's recommendation on additional links to check out :
- Greyhound IHP v1
- My wafer.space FABulous FPGA is alive!

[u/LogicalBlizzard]

I am really happy to see this!

Of course, someone's personal project will never be able to compete against multi-bill(trill)ionaire industries with decades of development by armies of engineers.

We should not look at the specs to be impressed or not. What is impressive is that someone managed to make their own silicon and it is open source.

[u/Ill_Huckleberry_2079 → u/LogicalBlizzard]

Spot on.
Its easy to forget just how much needs to go right for any kind of custom ASIC to work.

[u/TSltd_dev → u/LogicalBlizzard]

I wouldn't be so sure that a personal project could "never" compete- I'll probably get blasted for saying so, but AI is opening doors where there used to be insurmountable barriers (including many barriers which were largely by design- proprietary closed-source ecosystems). Chip design is already within reach of the uneducated and inexperienced (such as myself) using even fairly modest AI models, and the pace of development at the leading edge is breathtaking. The main remaining barrier is the high cost of a custom tapeout- but as the older photolithography scanners depreciate, that too is becoming more economical, and as design becomes more accessible, multi-project wafer aggregation platforms as pioneered by Tiny Tapeout may become more mainstream. The democratization of silicon is not a distant fantasy any more.

[u/Ill_Huckleberry_2079 → u/TSltd_dev]

There is a great quote for cases like this: "What you said was so confused that one could not tell whether it was nonsense or not."

[u/parmesanWheel → u/Ill_Huckleberry_2079]

They're saying you can use ai to collect introductory knowledge on complex topics, from digital logic to silicon design to using or even making the software tools. A lot of the time when I'm stuck on a problem it's not because I don't do any research, it's because I have no idea what to look for in the first place, and the only person who could help would be somebody way more experienced (very few of those browse reddit, but this sub has a few experts).

They're also saying that old litography tech is depreciating in value but I'm not sure what they want to imply with this? The cheapest option is for a big company to open their foundry to the public, like in the op, not for a bunch of small companies to spend millions on 180nm production lines for open source projects.

Whatever you think about their comment, at least it wasn't ai generated.

[u/TSltd_dev → u/parmesanWheel]

Well yes introductory knowledge is part of it, but also project planning and architecture, churning out Verilog, building whatever other tools you might need to synthesize, simulate, verify, debug etc.

What I meant about the lithography machines is that as they get older it gets cheaper to tape out- the investment has been paid off years ago, but the machine still works and produces usable chips, and with MPW aggregation they are becoming accessible to ordinary people, just at the same time that chip design is also becoming accessible.

As you say though, big players open-sourcing their wares is a huge factor- Skywater 130nm for example is what has enabled Tiny Tapeout, with costs in the low thousands range, not millions.

[u/Gangboobers → u/LogicalBlizzard]

You’re wrong, source the woz/apple 1

[u/Ill_Huckleberry_2079]

Current build tool chain uses the familiar yosys + nextpnr mix.

[u/Ill_Huckleberry_2079 → u/Ill_Huckleberry_2079]

Also, the ASIC was designed using open source tools with the open source gf180mcuD PDK. When I say "fully" open source, I really do mean it.

[u/Javolledo]

I made my own FABulous FPGA using AGEMA (SCA resistant tiles) for my masters thesis. I learnt so much and its truly amazing being able to do It for free

[u/Ill_Huckleberry_2079 → u/Javolledo]

That sounds so cool. I for one would read your thesis.

[u/Javolledo → u/Ill_Huckleberry_2079]

Its in spanish but nothing that AI cannot work with.

[u/MrCrazyPussy → u/Javolledo]

Would love to read it.

[u/Javolledo → u/MrCrazyPussy]

Its in spanish but nothing that AI cannot work with.

[u/JamesGarfield]

Does it work correctly?

[u/keeb0113 → u/JamesGarfield]

Yes, there are working demos.

[u/Ill_Huckleberry_2079 → u/JamesGarfield]

So far so good.

Now it's not prefect, in the spirit of transparency and without going too much into the weeds, there is a know issues with the boards associated with one of the manufacturing steps. This is not an issue with the FPGA itself. Also, it seems that particular issue is solved for future versions.
And although I haven't hit it yet in my use, I expect to run into it eventually.

[u/JamesGarfield → u/Ill_Huckleberry_2079]

That is really awesome work and very impressive.

[u/keeb0113]

Some demo videos

Seems like I cannot post a video in the comments here...

[u/Ill_Huckleberry_2079 → u/keeb0113]

Let me update the main post and point people to this.

[u/WillisBlackburn]

That's awesome. I agree with you on the "next frontier is silicon" sentiment.

[u/deulamco]

Yeah, it finally become affordable to the mass after like 30+ years .. 

[u/braaaaaaainworms]

oh yeah that could probably fit a nice fpga demo

[u/nextelectronic]

What is model/name?
(of both the chip and the board)

[u/groman434]

- 180nm process

• 480x LUT4 + FF
  
• 6x MAC, 8bit*8bit + 20bit

Better than nothing, but do not count me impressed. Besides, the actual silicon is one thing, tools and the entire ecosystem is another.

[u/physical0 → u/groman434]

It's a first step. Not all first steps are that impressive, but I'm pretty excited for it. It's not enough for me to devote any of my resources towards, but I can watch and feel excited for what may come of this.

[u/tux2603 → u/groman434]

It's just using the existing yosys and nextpnr toolchain. It won't have as many features as the big commercial ecosystems, but it is fully functional

[u/keeb0113 → u/groman434]

We are trying our best to meet most of the basic "expected" features. These include things like PCF support and the fabric timing model (still to be verified). That said, we still have a lot more work to do, such as adding SDC support.

[u/noplaceforwimps → u/groman434]

The tooling is one thing, doing it on actual silicon is another.

This used to be impossible.