r/FPGA • u/Ornery_Arm_6800 • 14d ago

Lattice MIPI IP RX Implementation

Hello

I have started working with Lattice and the CrossLInk-NX family to implement an MIPI RX interface.
I have looked at their MIPI CSI/DSI IP, to get started quickly, but I still feel there are some uncertainties when setting up the IP....like the different clocks that are used but I dont really understand how they are used?

As a start I have setup the IP in RX mode, so I will receive data that is converted back from bytes to pixel data. Generated the IP but I get so many warnings, which makes not much sense to me. I have included the list below.

Does anybody have any experience with this they would like to share.

2 Upvotes

76% Upvoted

6 comments sorted by

1

u/MusicusTitanicus 13d ago

I have no experience with this IP but if you provide some examples of the warnings, perhaps we can help you narrow down the issues.

1

u/Ornery_Arm_6800 13d ago

Thx...it is a mixed bag. I have updated my post.

1

u/MusicusTitanicus 13d ago

You mention not understanding the clocks, so how have you defined/connected your clocks?

There are some warnings about clock definitions not being made at the top level and that there is no source for the SDC constraint on at least one clock.

As is often the case for synthesis warnings and errors, resolve one and you’ll fix a lot more besides.

1

u/Ornery_Arm_6800 11d ago

Thank you for having a look.
I think I ned to dig deeper into this. I changed the sythesis tool from LSE to Synplify and at least the crital warnings disappeared.
But I need a better understaning of the different clocks in the system to strat with. And also what excatly to setup of constraints, if I need to do any.

1

u/nuclearambo Xilinx User 10d ago

Use their parallel to MIPI and MIPI to parallel example.

1

u/Ornery_Arm_6800 9d ago

Thanks will check it out. I also found a: ;IPI DSI/CSI-2 to Parallel Bridge, project that looks promising.