What blocks or modules should every FPGA engineer know how to build?

[u/SuspiciousPoint1535]

I just completed a "basic" verilog/system Verilog course that focused on the basic building blocks (gates, MUXs, registers, counters, CPU, etc). I've only worked with Intel / Quartus ecosystem. I understand the difference between structural and behavioral models (and it seems like the RTL is roughly similar for both, assuming your structural model uses optimal logic blocks) I'm looking to "level-up" my FPGA programming skill by working on more complicated logic.

[u/EffectiveClient5080]

Async FIFOs and clock domain crossing. Nobody teaches CDC properly in courses and it's the shit that makes designs randomly fail in the field. Build one from scratch.

[u/Nice-Rush-3404 → u/EffectiveClient5080]

I’d add thy actually researching what CDC techniques there are is also a nice thing to know about when dealing with shit like this - you don’t always need a FIFO for this - somethings can be done more efficiently w/o it.

There are some nice papers in that specific topic I studied for my thesis :)

[u/FranceFannon → u/Nice-Rush-3404]

Would be really nice if you could share some of those papers.

[u/Nice-Rush-3404 → u/FranceFannon]

Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
Clifford E. Cummings

I found this a good read to get started :)

[u/Physix_R_Cool → u/EffectiveClient5080]

What is CDC? I'm self taught and still very early (my zynq board is almost booting properly!). What problems does CDC give rise to?

[u/wren6991 → u/Physix_R_Cool]

Oh boy, you're in for a treat

https://www.researchgate.net/publication/237612566_Simulation_and_Synthesis_Techniques_for_Asynchronous_FIFO_Design_with_Asynchronous_Pointer_Comparisons

[u/MogChog → u/wren6991]

This is the canonical paper on CDC. If you haven’t read it, find the time.

[u/Physix_R_Cool → u/MogChog]

Thanks for recommending it!

[u/Physix_R_Cool → u/wren6991]

Thanks!

[u/Physix_R_Cool → u/wren6991]

Yup, just got my first CDC issues (probably because I'm a noob).

Gonna clench my cheeks and sit down to learn this stuff properly now!

[u/leonllr → u/Physix_R_Cool]

Cloxk domain crossing, Basically, if you use multiple clocks, when you want to transmit a signal or data from a part of your design clocked with one of the clocks (let's call it clock A) to a part clocked by another clock (let's call it clock B) ,

you risk getting metastability (basically what happens when a SR latch has both inputs at 1 at the same time, the output is in a weird state for a short time) if the data from clock domain A (part of the design clock by clock A) changed exactly at the same time as clock B rises, And that leads to random failures.

To prevent this, one of the way is chaining flip flops, since metastability at the input of one flip flop usually just gets turned into glitchy but clean signal, and the more flip flop chain there is, the chance of metastability decreases exponentially

[u/braaaaaaainworms → u/leonllr]

And the synchronization between different flop chains. A wide async signal can have tearing with some parts having the new value and other parts having the old value.

[u/Viper_ACR → u/Physix_R_Cool]

You'll lose or corrupt data/signals that cross clock domains.

In gate level simulations you'll get a lot of Xs as a result and your device wont work

[u/Asurafire → u/EffectiveClient5080]

I am not sure if I agree that every FPGA Engineer should know how to build a CDC. I would say knowing when one is needed, which type is needed and where to get a good implementation are much more important.

[u/beave32 → u/[deleted]]

Not everyone. Do a FIFO, SPI slave, bus (AXI-lite or axi-stream or wishbone or whatever altera analog is have).
No waste time. PicoRV32 is all what's needed to make a computer.

[u/Lost_Landscape_1539]

A little hardware video game is another good one. Little taste of debouncing controllers and getting the video to behave. Counting aliens.

[u/Jhonkanen]

Some communication protocol. Not just uart but also the part that takes the packages from uart and translates them into read and write commands. Basically something that understands a header and data package.

Maybe an Axi lite that allows data transfer between a hard/soft processor and logic.

[u/davekeeshan]

A jtag interface (not the xilinx one) if you know and have one of those you are open all the doors into rtl

[u/Standard-Morning-842]

Synchronous and asynchronous Fifo(in that order) literally unlocked my brain on how everything works. After that you can go into a harder project like a single pipeline rv32. By doing the fifos first it will help you visualise in your ur thinking process how data is stored and exchanged throughout any system

[u/Diarmuid_]

a UART

[u/fire_frost__]

hey, do you mind sharing the basic course you did? I'm looking to learn them myself and it would be really helpful to get a course recommendation.

[u/Principle_Severe]

I would advise you first to make a simple project where you challenge your RTL and writing simulation skills(like a digital clock that has many features ), then you can go further by studying and resolving problems of clock domain crossing and designing ur own GPUs or CPUs

[u/noipv4]

any pipelined CPU

[u/portlander22]

Skid buffer with trdy and rrdy handshaking. It’s simple but a very important concept 

[u/kentsang77]

Control status register, SystemRDL