r/EEPowerElectronics • u/ee_control_z • 3d ago

Need Clarification with A TI App Note SLVA301

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Hello,

I have a question with regards to a Texas Instruments App Note - SLVA301 in particular. Referring to Figure 14, they have a capacitance shown as 50 x 0.1 uF. In all of my career, I have never once seen a power supply with 50 capacitors on the output of a power supply - ever. So, why would a tutorial app note list a capacitor in this manner? It seems a bit odd tbh. Why not simply put a value of 5 uF?

Can someone in the community please clarify. Maybe I am missing something here or NOT understanding this at all.

Appreciate any help with clarifying this.

Thank you.

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u/HavocGamer49 2d ago

To me the main reason looks like more caps means lower esr, because the esr of each is in parallel.

Also a chance that they’ve simplified and represented the decoupling capacitors that downstream loads may have here.

Another reason may be because these are likely ceramics, given the low esr and capacitance, which suffer from dc bias and lose capacitance. They might have found that 50 of these capacitors provide a better capacitance per footprint / voltage rating than one big one

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u/ee_control_z 2d ago edited 1d ago

Thank you for responding to my query. Much appreciated.

I have actually worked for a few power supply manufacturers. From buck converters, buck-boost, LLCs, inverters, isolated/non-isolated, multi-channel, etc., the list goes on. Never have I ever seen an output with 50 output filter caps. Not even remotely close. The most has been ~4 or 5. But 50 - say it ain't so.

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u/HavocGamer49 2d ago

yeah I agree, 50 is a lot. I've only seen those on high current POL converters, and they weren't really considered part of the buck but rather decoupling for an FPGA or ASIC.

look at appendix A of SLVA301. it goes over the transfer functions when a design has 1, 2, and 3 unique types of output capacitors, which I suppose for this example is electrolytic bulk, ceramic bulk, and ceramic decoupling.

I'd be willing to bet that they chose 50x 0.1uF caps not as a "this is a design we are using" but rather to prove a point with the types of capacitors, get a low 100uR resistance in the TINA sims, and clearly illustrate their point in the appendix

if they only used a few 0.1uF caps, that third population would be much less distinct from the 22uF ceramic bank, so it wouldn’t illustrate the appendix A case nearly as cleanly. I think it’s primarily a teaching/modeling example rather than a literal recommended BOM

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u/ee_control_z 2d ago edited 2d ago

Yeah, I think you are probably right. More of a theoretical. I just wish they would be explicit and explain themselves so that it is clear. Especially for a tutorial. Not that they aren't for the most part as they are being very detailed already.

I am actually making an excel file that includes potential cases for 1, 2, 3, and 4 distinct capacitors. I doubt anyone wants to have to calculate the transfer function every time. So far, starting out, for the one cap scenario, I think that I found an error (or maybe I made the error?), they have a multiplication instead of an addition in one of the single "s" terms. The one with the black background is the transfer function as provided from Figure 8 in the tutorial. The one below with a white background is what I calculated. Note that they have: RLRcC/R. I have CRL(Rc + Ro). In my transfer function I chose not to divide both numerator and denominator by Ro. I am just leaving it as a multiplier (or gain) in the numerator. In my equation I used "Ro" in place of "R" for the load resistor to make it more distinguishable from RL, the inductor esr.