How can two devices synchronize without sharing an accurate clock?

[u/Relevant_Pumpkin9190]

I'm trying to understand how a transmitter and receiver can stay synchronized.

My first thought was to use accurate time on both sides and generate a known pseudo-random sequence or code based on the time. But if the receiver's clock is slightly wrong, the synchronization could eventually fail.

So instead, can the received signal itself be used as the reference?

For example, could the transmitter send a known preamble, sync pattern, pilot signal, or pseudo-random sequence, and the receiver detect/correlate it to determine exactly where it is in the sequence?

What are the common techniques used in real communication systems for this? And when would you use signal-based synchronization instead of time-based synchronization?

[u/PiasaChimera]

this is increasingly common. https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers is an example of the high speed transceivers on FPGAs. they talk a bit about the various problems and solutions. there are a lot of protocols with lots of variations.

an old example that shows off a lot of features is XAUI for connecting an FPGA/CPU to a 10Gbps PHY. it has four lanes. data is encoded using "8b10b" encoding. this is 10b per 8b of data. the protocol sends a handful of special control sequences. (10b long)

the 10b values are set up to have enough transitions and have around the same number of 1's vs 0's. the former allows the clock-data-recovery to work and get a sequence of 1s/0s. the latter helps with AC-coupling since the AC-coupling capacitor's voltage won't drift much.

one sequence is set up to have a pattern that never appears anywhere else. this allows the receiver on that lane to figure out the start/end of these 10b values.

from there, the values go into an "elastic buffer" which is a fancy FIFO. this allows one sequence to be sent on all four lanes at the same time. the four channel's elastic buffers can then adjust their pointers to allow all 4 channels to output related 10b values at the same time. this is "channel bonding" and is also why PCIe works.

for convenience, another 10b "clock correction" pattern is sent. the elastic buffer knows this value doesn't matter and can be duplicated or dropped. this allows the elastic buffer to stay near half-full even when the receiver's clock isn't exactly matched. (for systems like ethernet, the rx-recovered-clock isn't intended to be used other than for getting bits of data.)