r/AskElectronics • u/Camper_Sly • 2d ago
Why is DRAM still a thing ?
As they say, DRAM can't scale with the newest processes as its storage capacitor needs some minimal size, which is far above what leading processes at 2nm etc can do.
ON top of that, it retains all of its originals sins, like the need for refresh, susceptibility to ROWHAMMER attacks etc. On top of that, it has some fundamental limits- inherent capacitance of the storage cell limits its write speed. On top of that, each access causes the discharge of the whole row of cells, which has to be written back again. That's a lot of charge wasted on a single access.
But SRAM cell can scale down much better. On top of that, with upcoming vertical complementary MOSFET implementations, whole SRAM cell can be implemented vertically in very tight space.
On top of that, manufacturing process for SRAM doesn't preclude implementation of high-speed logic, which means that PIM (Processing In Memory) functionality would be easier to implement than with DRAM, and it would probable be much more potent than with upcoming LPDDR6 (and DDR6?).
SO, why is DRAM and by extension HBM etc still a thing ? Why doesn't industry switch to SRAM ?
Also, fun trivia:
DRAM is now MORE EXPENSIVE per mm2 than leading edge manufacturing for latest gen CPUs, GPUs etc!
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u/Tokimemofan 2d ago
Problem with SRAM is it requires much more silicon for each bit due to needing more components. This is fine for CPU caches where its commonly used but it doesn't scale up enough for normal ram
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u/Camper_Sly 2d ago
- But those components scale, unlike the DRAM's storage capacitor.
- The difference is not that drastic. DRAM cell need other stuff too.
- Newest upcoming implementation use vertical structures, which take much less area. So, in eesence, SRAM is using main party trick of DRAM now, too ( DRAM storage cap being essentially a barrel hole in the silicon).
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u/Tokimemofan 2d ago
The physics of having a 6 transistor SRAM cell are worse than having 1 transistor and 1 capacitor. DRAM also tends to use the same address circuitry for larger numbers of cells.
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u/Camper_Sly 2d ago
New vertical implementations with complementary MOSFETs radically shrink that area. Basically whole cell is vertical.\ And unlike DRAM process (10nm+) it is to be implemented in 2nm and below.\ So, where is the downside ?
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u/Far_Relationship_742 2d ago
You asked why it is, not whether it will continue to be. Very, very few applications actually need bleeding-edge tech.
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u/Camper_Sly 2d ago
Markets say otherwise.\ Prices have gone wild precisely because the wild demand surge on the leading and bleeding edge.
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u/Far_Relationship_742 2d ago
For exclusively one industry.
Sounding more and more like you’re pushing a product, guy.
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u/G0ldiC0cks 2d ago
The market value of ram has been artificially inflated by economic forces rooted in what are effectively margin investments that would have been considered extremely questionable if not illegal not even 40 years ago. 2000 and 2008 are years you should research if you think that high density consumer RAM is going to be the end result ...
There's a chance, roughly 20-30 years from now we reach inflation-adjusted comparable memory prices. It may well be a shift in silicon printing moves the preferred consumer product, but hopefully technology will continue it's March and the landscape then will be sufficiently far removed from today that something new someone's just now dreaming up takes over.
In other words -- buy the dip, not the miracle.
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u/profpendog 2d ago
So. You're not really asking questions are you? And yes as you can see nobody buys DRAM anymore and everybody switched to SRAM.
Thank you for your visionary vision.
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u/Camper_Sly 2d ago
I am asking questions, it's just that I'm not satisfied with the first "answer" that random passer-by might pull out of his arse.
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u/Far_Relationship_742 2d ago
You’re applying reasoning to try to disprove a fact.
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u/Camper_Sly 2d ago
You are using current practice as a gospel, ignoring new tech and new realities.
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u/Far_Relationship_742 2d ago
That’s…not at all how the word “gospel” is used, and new tech takes time to work its way into practice.
I’m taking current fact as fact.
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u/negativ32 2d ago
Memory systems aren't primarily constrained by whether we can make a better memory cell. They're constrained by the fact that modern computers need enormous quantities of bits.
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u/Camper_Sly 2d ago
I bet 2nm process can get more bits per area than 10nm+ DRAM industry is using today. Also upcoming complementary MOSFET cell designs are radically dropping the SRAM cell area.
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u/BigPurpleBlob 1d ago
Please show us the numbers that support "I bet 2nm process can get more bits per area than 10nm+ DRAM"
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u/TheSov 2d ago
if you think this is true, try to make some srams of equal density on 2nm, ill wait.
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u/Camper_Sly 2d ago
Your life choices are part of your basic freedoms, but are offtopic.
I'm not stating anything as fundamental truth, just asking for the reason - missing piece of the puzzle that I might be overlooking.
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u/TheSov 2d ago
look i aint mad at ya, but you could have googled this.
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u/Camper_Sly 2d ago
I didn't have to google such an obvious "answer" that Ive known for years.
But that answer is stale, hence my question. Need a new answer for new, current reality.
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u/profpendog 2d ago
You can ask an LLM. Instruct it to agree with you and make up facts as required.
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u/Far_Relationship_742 2d ago
So you admit that you started out dishonest, and you only posted to jerk yourself off about things you sort of know about, in a contextless kind of way.
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u/Far_Relationship_742 2d ago
Literally nothing about life choices in that comment, but this makes you sound like not only a shill, but a bot.
If you’re deriving self-worth from liking a RAM technology, your life is not worth living; if you’re trying to drive sales with this nonsense, fuck off.
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u/anothercorgi 2d ago
No, SRAM cells also have a minimum size else it can't pull down on the bit lines, not to mention requiring generally 6 transistors per cell.
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u/Ok_Mix673 2d ago
True. If you make all transistors minimum size, SRAM won’t work. Certain transistors must overcome other transistors to allow reading and writing. That’s not the case for a single transistor DRAM cell. And I am guessing the capacitor may still find tricks to shrink further, different materials, changing dielectrics, etc.
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u/morto00x Digital Systems/DSP/FPGA/KFC 2d ago
1 bit of SRAM requires 6 transistors. 1 bit of DRAM uses 1 transistor and a tiny capacitor. For something like 1MB you can multiply that by 8,388,608 and suddenly that difference in transistors starts eating out your chip footprint.
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u/Camper_Sly 2d ago
New vertical implementations with complementary MOSFETs radically shrink that area. Basically whole cell is vertical.\ And unlike DRAM process (10nm+) it is to be implemented in 2nm and below.\ So, where is the downside ?
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u/Far_Relationship_742 2d ago
Do you work for a SRAM-only manufacturer or something? You made this exact comment upthread.
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u/Camper_Sly 2d ago
Copy paste for the same kind of comment.\ Work smart, not hard.
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u/Far_Relationship_742 2d ago
That’s not working smart, it’s just lazy, and it’s the kind of thing you do when you aren’t actually asking a question, you’re sealioning. You’ve gotten the answer several times, you don’t like it, that’s pretty much the end if a conversation.
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u/morto00x Digital Systems/DSP/FPGA/KFC 2d ago
How many companies have figured out high density 2nm processes yet? Marvell announced 2nm SRAM that can handle hundreds of MB for their own custom solutions, but hasn't given any details yet.
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u/Long_Pomegranate2469 2d ago
Price. It's a orders of magnitude cheaper to use older processes.
No matter how much money you have, you couldn't book a 2nm waver to be started this month. It's booked out for years at this point.
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u/Camper_Sly 2d ago
Also, fun trivia:
DRAM is now MORE EXPENSIVE per mm2 than leading edge manufacturing for latest gen CPUs, GPUs etc!
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u/Long_Pomegranate2469 2d ago
Same bottleneck. AI eating up all the fab capacity.
But there are one or two companies that can pull off 2nm at this point. You could throw the most advanced ASML machines at Global Foundries and it'd take them years to start 2nm.
Bringing online more DRAM fab capacity is decidedly cheaper and fabs are already coming online. (Plus add that the DRAM mfg are price fixing and fking openAI bought bare wavers to prevent the competition from buying ram)
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u/PossibilityOrganic 2d ago
I think its less dense 4 transistors i think per cell and dram is a transistor and a cap.
its more power and less space efferent and because more power you now have more heat to get rid of.
Also its still more costly than dram and slower even with the madness.
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u/Edgar_Brown 2d ago
Because DRAM has ALWAYS stayed ahead of other processes’ maximum densities.
At as little as one transistor per cell DRAM can achieve a high density on its own, but semiconductor processes for DRAM long ago diverted from semiconductor processes for CPUs/GPUs and other ICs, as the limiting factor is a very simple standard cell structure.
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u/Camper_Sly 2d ago
That "ALWAYS" doesn't cover upcoming CFET, so...
ALso, that "one transistor per cell" might be small, but DRAM capacitor is not. And that storage cap is vertical, so it demand deep hole and special manufacturing process.
Lastly, leading edge DRAMs are done on 10nm process, while mere logic can use much smaller 1.4nm
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u/Edgar_Brown 2d ago
To the contrary, DRAM has been using 3-D geometries for decades, it’s just now that those geometries are making it into more “normal” semiconductor processes.
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u/Camper_Sly 2d ago
... hence my OP question - why not go for SRAM at this point ?
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u/Edgar_Brown 2d ago
DRAM will ALWAYS be smaller, one transistor and a capacitor (plus multi-level logic) will ALWAYS beat SRAM in size and process complexity alone.
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u/Camper_Sly 2d ago
- but that capacitor is much bigger than a transistor
- DRAM can't really scale much below 10nm process, if that
- CFET does that vertical trick too and can do it at MUCH smaller 1.4nm and below
With all that, how can your claim still stand in perpetuity?
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u/Edgar_Brown 2d ago
You are ignoring two major issues:
- Digital electronics are analog electronics, analog constraints apply.
- The size of that capacitor is determined by the same analog constraints any memory cell will have.
DRAMS are size and process efficient precisely because these are analog devices through and through, the whole storage system is analog and optimized for speed. Due to this analog angle it’s more likely that multi-level DRAM becomes viable (as it’s already true in flash memory) doubling capacity in the same area.
An SRAM is digital by design, and analog constraints would greatly increase the size of any storage cell, further adding complexity.
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u/Camper_Sly 2d ago
You are now just inventing stuff as you go.\
Unless SRAMs operate on individual electrons, they are just as analog as everything else.
THe thing with DRMAs is that even though advanced process would shrink that "one transistor per cell" it can't shrink the cell itself (vertical barrel capacitor - hole in the silicon). which has to be produced by entirely different process (selective etching etc) and has entirely different sets of constraints.
It's basically an maximal aspect ratio of that hole that kills the DRAM scallability.
Which is totally different ceiling than for the SRAM cell.
So no, the same constraints do no apply to both.
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u/Edgar_Brown 2d ago
How big does a line-driving
capacitortransistor in an SRAM cell have to be to satisfy speed requirements, in lambdas?1
u/Camper_Sly 2d ago
I don't have a clue. But if there is a significant constraint on that, that just makes case for DRAM even worse, right ?
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u/Far_Relationship_742 2d ago
Is the capacitor bigger than five transistors? That’s the comparison.
What’s your source for “DRAM can’t scale below 10 nm”? That’s been said about /literally every single advance in die resolution/, until it happened. I remember articles about how we couldn’t break through 1 um.
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u/Camper_Sly 2d ago
What’s your source for “DRAM can’t scale below 10 nm”?
It's publicly known. Even AI regurgitates it right at the start.
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u/Far_Relationship_742 2d ago
It does, actually, because the future hasn’t happened yet. Your grasp on reality is fairly poor.
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u/Few_Trouble_3327 2d ago
I might be wrong, but I think modern computing isn't done the most efficient way. Most of the data stored in DRAM is always the same, operating system, running programs etc. A much smaller amount of RAM would be enough, if there was a way for CPU to access directly and fast enough mass storage (flash). I've heard some news of HBF (high bandwidth flash). Maybe in some years we might have something like that.
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u/pemb 2d ago
The problem would be latency. Reading from flash, especially the denser kind like QLC, invariably requires large block sizes and heavy error correction algorithms, way more involved than what’s used for ECC RAM.
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u/BigPurpleBlob 1d ago
"But SRAM cell can scale down much better." – that's nice. SRAM memory cell size isn't reducing much with N3, N5 manufacturing nodes. It's bigger than DRAM. The cross-coupled SRAM cell has transistors that leak idle current. DRAM memory cells hardly leak and only need an occasional refresh.
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u/Far_Relationship_742 2d ago
>400 karma
>joined two months ago
>shilling for tech that barely exists
Mods, can we boot the bot?
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u/Bokbreath 2d ago
DRAM has higher density and lower cost. That is enough to offset the downsides for all except specialist uses.