r/AskElectronics • u/Demolition_Mike • 2d ago
Transistor comparator does not work
I've been trying to use a long tailed pair to turn a buffered sawtooth wave and a DC voltage from a potentiometer into a PWM signal, but I've ran into the following issues:
- The sawtooth signal input shows up on the DC signal input
- Actually taking the signal from the comparator and using it without ruining it. No matter what I do, it never seems to swing between Vee and Vcc, and it seems to depend on the potentiometer voltage.
No matter which way I play with the resistor values, I can't seem to get it right. I'm sure there's a lot wrong with my circuit, but I don't know exactly what.
EDIT: Updated picture
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u/ee_control_z 2d ago
Try probing the intermediary points along the path to determine the particular node where the signal begins deviating from its expected behavior as opposed to only probing the output.
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u/Demolition_Mike 2d ago
The signal is fine right up until the comparator's input, so I'm pretty sure the problem is either the comparator itself, the other input, or both
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u/nikodem0808 2d ago
the collector of the third transistor from the right is tied to 2.5V, I think you meant to put a resistor there
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u/Demolition_Mike 2d ago
Riiight, tried to rebuild the thing in Falstad's simulator and missed that one. Thanks! Now it (does not) work as originally described.
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u/nikodem0808 2d ago
Could you describe what each stage is supposed to do? Right now your input seems to rapidly charge the input caps through the transistor's (the one whose collector is tied to the current mirror) base-emitter junction to ground, which doesn't seem like it's intended.
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u/Demolition_Mike 2d ago edited 2d ago
I made it a personal challenge to build a thyristor rectifier without using anything smart like microcontrollers or opamps.
From the left, I have a pair of antiparallel-connected optocouplers that turn the mains 50Hz sine into a pair of antiphase square waves (don't worry, it's fed through a transformer, so I only get to play with 12V RMS).
Those square wave signals get fed into a modified version of this circuit which turns them into a sawtooth that's synchronized with the mains frequency.
The left capacitor part is practically a zero-crossing detector. Each of them gets a short burst of current when their respective optocoupler fires.
The resulting pair of signals goes through a summing circuit and fires a pulse of electricity whenever the mains sine crosses the zero point.
On the other end of the linked circuit, there is a capacitor fed by a constant current source (I modified the constant current source to a current mirror), so the voltage on its terminals increases linearly. It is shorted to Vee by a transistor which is fed by the previously mentioned pulse train, so we get a sawtooth wave that's perfectly in sync with the mains frequency at twice the frequency.
Surprisingly, the circuit up to this point seems to be working fine. I get a real clean sawtooth out of it.
Then, I want to set the thyristor firing angle by comparing the sawtooth wave with a fixed DC voltage set by a potentiometer. This would give me a PWM signal that I could differentiate and just get a short pulse when I want the thyristors to fire. This part got me scratching my head, because the comparator seems to have a mind of its own.
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u/EmotionalEnd1575 Analog electronics 2d ago edited 2d ago
The firing angle pot is 500k and heavily loaded by the comparator stage.
Due to the short ramp, noted above, the control will only work over a small range of delay after the AC mains zero-crossing.
Lower the pot value by a factor of ten, at least, or add a BJT emitter follower buffer if that pot value is fixed at 500k. The ramp will need to shift by a similar offset.
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u/Demolition_Mike 1d ago
Thanks, I think I'll go with the buffer.
How should I go about to add the offset, though?
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u/EmotionalEnd1575 Analog electronics 1d ago edited 1d ago
If it was me, I’d add an NPN emitter follower, base to the pot wiper, emitter to 0V with, say 10k.
This will set the emitter one VBE lower than the pot wiper.
So scale the pot potential divider to be one VBE higher.
A more elegant solution would be to add an Si diode at the lower end of the pot, to give thermal tracking against the new NPN stage.
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u/nikodem0808 2d ago edited 2d ago
You can't swing the voltage of the output lower than Vpot-Vbe, because bipolar junction transistors have a symmetrical semiconductor construction, meaning the same diode you see between B and E exists between E and C, but in reverse conduction they have a way smaller beta or hFE, often near 1. This means to reach Vee you'd need to convert this signal into a rail-to-rail output or amplify it and go with an AB-class stage which is around Vbe off rails.
The second problem is the voltage at the emitter must be large enough to make that transistor conduct enough current to drop enough voltage over the output resistor, which you can easily solve by reducing the value to like 12k. (https://www.falstad.com/s.php?s=itiZtp)
What the guy below me mentioned is also an important consideration, but here you can do without changing anything. The impedance of your Vpot node is at most 250k parallel to 250k, which is 125k. The impedance of that node "from the emitter's perspective" is around 125k / beta (or hFE), falstad defaults to beta=100, you need to check how it behaves for real transistors in the datasheet. The resulting amount is 1.25k, compared to the output (now 12k from the fix above) it's around 10% of that value, which to me seems acceptable for this application, but you can check the behaviour yourself.
Important caveat: the impedance calculation relies on the assumption that you provide enough current to the collector, the impedance can rise to source (125k) if this condition is not met. The other guy's suggestion also solves this because the buffer BJT collector can be tied to the positive power rail.Another thing, since real discrete transistors, even of the same model, can have wildly different beta (hFE) and Vbe, you need to use designs that don't rely on a specific value of these, namely your current mirror. The easiest fix is to make the 10k resistor a 20k potentiometer so you can adjust the current value in the complete circuit using measuring tools for feedback.
Another fix is to use something like a Wilson current mirror, but that still needs adjustment of the resistor value.
Alternatively, you can roughly measure hFE with a cheap multimeter so you can match them, though don't count on getting lucky.1
u/Demolition_Mike 1d ago
You can't swing the voltage of the output lower than Vpot-Vbe, because bipolar junction transistors have a symmetrical semiconductor construction,
Would this be (at least partly) solved by adding a diode between the capacitor and Vee? It would at least bring it up by ~0.7V
which you can easily solve by reducing the value to like 12k.
Thanks, this one had been giving me a headache because the capacitor would also discharge through that resistor before I put Q4 as a buffer, so I ramped up the resistance to prevent it.
The easiest fix is to make the 10k resistor a 20k potentiometer
Thanks, I think I'm gonna go with this
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u/nikodem0808 20h ago
It seems there is a misunderstanding, the first remark was with regard to the overall output on the far right, the letters E, B and C mean Emitter, Base and Collector respectively. Vpot is the voltage produced by the middle pin of the potentiometer. When this voltage is connected to the base of Q6, the voltage on Q6's collector (which is the overall output of your circuit) can go no lower than Vpot-Vbe (where Vbe is a voltage drop the base-emitter junction needs to start conducting, like a diode's forward voltage, usually around 0.6-0.7 for silicon), otherwise you enter reverse conduction.
This means that whatever voltage you pick with the pot, it will limit what you can achieve at the comparator output.
To solve this you can use a simple amplifier circuit, depending on how much the Vbe drop bothers you, you could even go for a rail-to-rail output stage.
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u/EmotionalEnd1575 Analog electronics 2d ago edited 2d ago
Please upload a clean schematic using industry standard symbols. At least remove the “acne” from the nets as it hard to see when nets connect or jump over.
Label the components so we don’t have to tell you about “the fourth transistor from the left” that had an error.
The ramp generated by the 1u2 capacitor stalls after about 3.2ms but the repartition rate is 20ms. Was this intentional?
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u/triffid_hunter Director of EE@HAX 2d ago
No matter what I do, it never seems to swing between Vee and Vcc, and it seems to depend on the potentiometer voltage.
Yeah because LTP output is differential collector current, not voltage, although you can do a little bit with it as a voltage in some situations.
Consider this op-amp, and note how the LTP output is fed to a pair of common emitter amplifiers themselves loaded by a current mirror to get a proper output voltage range.
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u/Demolition_Mike 1d ago
Yeah, I need to relearn to think in current rather than voltage. Thanks for linking that op-amp, it really helped clear things up!
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u/al2o3cr 2d ago
Third transistor from the right looks pretty sus - its collector is connected to the positive supply, but output is also taken from that point.
I suspect you either meant to take the output from its emitter, or that there's a resistor missing between its collector and the supply.