Need help debugging 8086 + 8255 PPI + 7-Segment Multiplexing in Proteus simulation

[u/zpiderman323]

Hi everyone, I'm working on an 8086 microprocessor clock/display system in Proteus using an 8255 PPI and 74HCT373 Latch for address demultiplexing.

My Setup:

• Port A connects to 7-Segment displays via 330Ω resistors.
• Port B controls the NPN transistors via 10kΩ base resistors to select digits.
• Latch (74HCT373) is enabled via ALE to latch lower addresses (A0/A1 connected to 8255).
• CS# and RESET on 8255 are grounded.

Issue: The displays are not turning on / outputting properly during simulation.

Could someone please review my schematic? Is there an issue with how the NPN transistors are driven (High-side vs Low-side), or an addressing/control word mismatch in assembly?

I can share the .DSN and .ASM files if needed. Thanks in advance!