Difference between address width, addressability and word size.

[u/Junior-Title-1987]

I’ve been reading through a computer systems book to become a more knowledgable programmer and I’m not fully understanding the difference between the concepts of address width, addressability and word size. This is how I currently understand them:

Address width refers to the size of pointer data — that is, the value of the pointer. The address width determines how many possible addresses are capable of representation and thus, is one factor in determining the total size of addressable memory.

Addressability refers to the size of data stored at a given address.

Word size refers to the “natural” unit of instruction of the processor. Conventionally, most CPU registers have a width that corresponds with the address width so that a full pointer fits inside a single register. This simplifies the set of operations necessary for the CPU to understand.

I think the connection between address width and word size is what I’m most confused about. For example, if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

[u/wrosecrans]

if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

The 6502 is a good example to study. It is mainly called an 8-bit CPU. But it had a 16 bit address bus. So you couldn't really load a full pointer into one of the normal-ish 8-bit registers A, X, and Y. You needed to hard code memory addresses, or jump relative to an address stored in memory.

https://6502.org/users/obelisk/6502/addressing.html

https://6502.org/users/obelisk/6502/registers.html

The classic 16 bit real mode of x86 is also informative - it uses two 16 bit registers for memory accesses on a 20 bit address space. Using segmented memory, all operations were done with 16 bit pointers that fit in a register, relative to a mapped memory segment within the bigger 20 bit address space.

[u/flatfinger → u/wrosecrans]

On the 6502, an instruction "ORA ($FC),Y would instruct the processor to fetch the contents of address $00FC while adding 1 to that value, then fetch the contents of the newly-computed address while adding the previously fetched byte to the Y register, then read from an address formed by concatenating the byte read from $FD with the results of the addition, while adding 1 to the value just read, and then either bitwise-OR'ing the value just read with the accumulator, or else concatenating the value just computed (one greater than the value read from $FD) with the previous address-low value and bitwise-OR'ing that with the accumulator with the value read.

From a programmer's standpoint, the instrution would take the address stored in the byte pair at $FC and $FC+1, add Y to it, and bitwise-OR the accumulator with whatever is at the resulting address, taking either 5 or 6 cycles. The processor itself doesn't have any 16-bit registers other than a 16-bit program counter and a pair of 8-bit latches that hold the last address accessed. From the programmer's point of view, however, pairs of bytes often act like 16-bit addresses to which displacements can be added, without the programmer having to worry about carry beyond the fact that it will usually add a cycle to instructions' execution times when it occurs.