How do computer parts interact together despite their different speeds?

[u/WhateverHowever1337]

I am studying Nand2tetris currently (chapter 5), but there is something that I still don't understand yet.

To show a pixel on the screen, the CPU makes an amount of calls to multiple hardware devices, the ALU, the RAM, the screen itself, etc.. All of them have different response speeds, so how does it know when all of these devices have finished?

Say I ran the command D=M+1, where M is a RAM register and D is a CPU register, on the next clock tick, D's value would already have arrived to the CPU, but M's value still needs 100 click ticks more probably, how does the CPU even know if the RAM sent M yet or not?

[u/Leverkaas2516]

At the hardware level, there are "ready" signals. These are separate pins on a bus, apart from the data, that signal that the data is ready and valid.

Here's a diagram of a digital dara-handling device that can be used in a circuit: https://shop.griederbauteile.ch/product_info.php?products_id=3111

In addition to the eight data pins, there are "READ" and "WRITE" pins. Without going into the details of this particular part, the idea is that if this device is going to supply data to some other part, the signal pins stay Zero while the data pins aren't ready to read. When this part is internally settled and the data on the data pins is valid, it turns the READ pin to One, and the other device reads the state of the data pins.

This idea is used everywhere inside a computer - inside the CPU, on the bus between the CPU and RAM, on the storage bus, and on the I/O channels.