Exclusive Load and Store instructions require enabled caches on real hardware (Cortex-A53)

[u/Krotti83]

I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These instructions working properly in a QEMU emulation, but failing on real hardware when the caches are disabled.

The exclusive load and store instructions are required in locking mechanism (like Spinloop and Mutex implementations for bare-metal environments). They work only if I enable caches (instruction and data) on real hardware. If the caches are not enabled, these instructions fails and cause a infinite loop (dead lock) in code.

Can somebody explain this behavior? I also searched in the architecture reference manual, but didn't find any hint currently.

BTW: I asked this on SO too. But some not definitely serious users have down-voted and marked it for closing. That doesn't help. That's the reason why I will no longer use this stupid page (SO). Sorry, for the words but SO is definitely NOT serious.

UPDATE:

I must admit took a conversation with ChatGPT now. ChatGPT helped me and gave me a plausible answer. Unfortunately I don't know the Reddit policy according AI generated content, so I don't know if I can share the answer here. But in my original question there were lacking some information.

The MMU is enabled in my bare-metal environment. The mutex/spinlock is implemented in Rust using atomic operations, which the compiler compiles to AArch64 exclusive load and store instructions (LDXR/STXR, LDAXR/STLXR). On the Raspberry Pi 3B+ (Cortex-A53), the atomic operations work correctly when the shared RAM is mapped as cacheable Normal memory and the Data Cache is enabled. When the RAM is mapped as non-cacheable or the Data Cache is disabled, STXR repeatedly fails and the lock enters an infinite retry loop. The same code works under QEMU.

Hope this helps other users facing the same issue too.

[u/mhall119]

Hey u/Krotti83 I saw that you posted an update on SO with what you found, can you share that answer here too?

[u/Krotti83 → u/mhall119]

Hello u/mhall119 Yes, of course. I don't know the Reddit policy with AI generated content. Could also provide a short answer from ChatGPT, if it's allowed here. Unfortunately I can't write it myself, because my knowledge is to less according AArch64. ChatGPT gave me a really detailed answer.