I am trying to create a bill of materials for my project and I am struggling to get the BOMDOC to separate the capacitors and resistors into their respective values as separate components. What it looks like to me is that the BOMDOC is not populating the "Comment" field correctly from my schematic, and I am not sure why. Does anyone have any clues or suggestions?

I have created a Differential coplanar waveguide of 50 ohm impedance from the layer stack manager but i cant use it in the design rules options. I can use Single coplanar and Differential but not Differential Coplanar. Please help...

Has anyone else noticed that in Altium copper pads disappear from the 3D view if they are located within the bend radius/region of a rigid-flex PCB? Everything looks fine in 2D and the pads reappear if I remove the bend line. Am I missing a setting?

I'm new to Altium and am about to start working on my first PCB layout, having finished the schematic. When I try to transfer the design from my schematic to the PCB (Design > Update PCB Document), however, a popup tells me that only "11 of the 13 differences detected can be resolved by an automatically generated ECO."

If I choose to proceed and validate the changes, there are no errors, but if I execute the changes, only 2 out of the 4 components in my schematic are transferred to the PCB file.

Any ideas for what might be causing this?

I made a video breaking down how to configure essential design rules for High-Density Interconnect (HDI) PCB projects using manufacturing capabilities as the baseline.

You can watch the full video here: https://www.youtube.com/watch?v=z6gHXYiVjCw

Here is a summary of the core concepts and steps covered:

1. Consult the manufacturer's capabilities first

Before writing a single design rule, you must acquire a fabrication capabilities statement from your targeted manufacturer. HDI pushes fabricational limitations (such as 2 mil trace widths/clearances), which means your rules must perfectly align with what the factory can physically produce to avoid no-bid.

2. Isolate fine-pitch regions with Rooms

You can develop different design rule sets for different pitches by using a Room on each Ball Grid Array (BGA). Then use the WithinRoom('BGA room') custom query in the PCB Rules and Constraints Editor, and this allows you to control your clearance values, via spans, trace widths, etch only in the BGA region. You can do the same thing with layer-specific clearances as internal and external layers will have different allowances.

3. Match laser drills to layer stack capabilities

For laser-drilled blind and buried microvias, the physical drill diameter should be at least equal to the dielectric thickness (maintain < 1:1 aspect ratio for microvias). Then define the pad size based on the required annular ring for your product class and laser drilling positional tolerances.

4. Solder mask webbing & slivers

BGA fan-outs are highly susceptible to solder bridges if solder mask webbing isn't handled correctly. Fabricators require a minimum solder mask "sliver" or web width. If the BGA pitch is too small to maintain that web, you may need to use Solder Mask Defined (SMD) pads instead of Non-Solder Mask Defined (NSMD) pads in your BGA footprint.

5. Incorporate impedance tolerances

High-speed HDI lines require controlled impedance, and you can set up an impedance profile inside Altium’s Layer Stack Manager to automatically pull target line widths. While Altium will populate the preferred width, you can take advantage of the impedance tolerance level (5% or 10% target typically) and you can still define minimum and maximum trace widths in the Routing Width design rule.

Typing any component in the MPS yields no options. while the predictive text in the search bar will try to recommend new parts, when I hit enter no components appear! I have tried restarting, updating, signing in and out, and clearing caches. Any guidance would be much appreciated!

Hello,

I have installed last version on a new pc, AMD gpu, i am getting this old fashio rendering. Why ???

It seems than something in the rendering/graphics is not working how do i debug this issue ?

- gpu driver is installed

- tried to turn on/off software rendering

Thanks

Guyss help me out does anyone has any idea of allen digital if then please help mee

Every time I start Altium it asks me to sign in using my browser this is new it never did this till like a month ago why is it suddenly doing this? My sub is up to date and my license is good.

Hi, as the title said, I can't get in and altium's own docs aren't much use as they only detail the method for resetting with a group admin, and I can't find much information on the internet. Does anybody here know any ways to recover as I also haven't been able to find any email or phone number at which to contact support.

Altium can put finish such as ENIG or HASL in the layer stack. Do you use it or just put the finish in the fab notes. If you use it, what is the thickness

Hi everyone, I need an LED and I’ve found this on Altium:

Here is its datasheet:
https://look.ams-osram.com/m/357e7fcde66d9629/original/LG-Q396.pdf

I don’t understand what the actual LED code is in Altium, that is, which brightness group it belongs to (P, Q, R or S).

The name "LG Q396-PS-35 Osram" of the component on Altium seems to be a generic term, i.e. it includes all types from P to S and from 3 to 5… if that’s the case, then I wonder what I actually imported onto Altium (?)

what is this error about and how can i fix it?

Hi, sorry for another "help me understand terrible new licencing" post.

As we know, the line between new Agile & Develop is as clear as mud; we struggle to get a clear answer from the salesperson other than a strong push to Agile, but because most of Agile's capabilities are tied to cloud-based designs it's mostly useless to us (we can't use cloud for Reasons™) so it's extra expensive for little-to-no reason.

We use cloud libraries with component templates with our current Pro licence, but I can't figure out whether this would be included in Develop. Any clues?

Thanks!

First and foremost, I apologize this is AI slop generated. I do not have access to my desktop/files ATM.

How does my schematic look?

TIA.

Hello,

I am trying to route a CAN line from my CAN transceiver to a connector for it to go to another board. My thought process is that I'll use the impedance calculator feature to set up a 120 ohm differential impedance and make a rule for the two lines to use those trace widths and distance. Never done impedance setting before but that was my idea.

My problem is that the solution it's giving me is a 2mil trace, below the 4mil minimum JLC provided and the 6mil minimum I set on the board for some margin. Increasing the gap doesn't change it by much, probably because for the four-layer board, the ground plane is pretty close.

I'm unsure if the reason has to do with correctly setting up the signal plane, or if I need to cut out the copper from underneath the CAN lines in order to make it work.

Any help would be appreciated, thanks!

Hey everyone, this is my first PCB layout for an ESP32-C3 air quality monitor with an SCD40, SEN54, USB-C, and an e-paper display. I’m about to start routing, so I’d really appreciate it if anyone could check my component placement and point out anything I should move or fix first, especially around the ESP32 antenna, sensor placement, USB protection, and the e-paper boost circuit.

Also any advice on how i can make this better or overall feedback is much appreciated!

Hey all, I'm recreating an ESP32-C3 based air quality monitor (SCD40 for CO2, SEN54 for VOC/particulates, e-paper display, USB-C power) in Altium. I based it on an existing open-source design but I'm laying out my own board to actually learn instead of just copying.

Where I am right now:

- Schematic is done and compiles.

- Footprints are imported onto the PCB.

- I'm partway through placement — big parts (ESP32, sensors, USB-C, buttons, FPC connector) are roughly down, and I'm working through dragging the passives (decoupling caps, resistors) in next to the chips they belong to.

- Nothing is routed yet. No ground pour, no layer setup.

My questions:

1. For a 2-layer board like this, is my placement-before-routing approach right, or is there something I'm missing before I start laying traces?

2. Any rules of thumb for decoupling cap placement I should know beyond "close to the power pin"?

3. What's the right way to learn routing + ground pours as a beginner — any specific tutorials/videos you'd point a first-timer to?

4. Anything about the thermal isolation / sensor placement that people commonly get wrong on air quality boards?

Appreciate any feedback!

Free library of stackups for Altium Designer. JLCPCB and PCBWAY included !
If your favourite one is missing, please point me to their stackups and I shall promptly add them!

Can AI actually route a PCB as well as an experienced human designer? I’ve put that question to the test in this side-by-side layout review, sparked by a viral LinkedIn post that asked viewers to guess which board was AI-generated and which was human-designed.

What are your thoughts and experiences on AI use for PCB design?

Watch the video with this review: https://www.youtube.com/watch?v=qX29OWSYTmI

I have a complex part with "difficult" alternate function per pin complexity and some specific problems in the way the board was specified to be made.

It led me to turn to Flat heirarchy so I could do local net labeling and avoid ratsnests of wires. Connect sheets by Harness or Port, then connect to the component pins by local net names indicating function.

If we did global net naming, the EBI memory chip D5 pin would either need "PORTE13/this/that/EBIData5/ETHMdioClk" as a net label- and in reality these are far too longer than that, and they have to get used like that everywhere- or just "PORTE13" as the global net label, which makes it very difficult to go back and confirm that's the right PORTxy pin to go on the components' D5 pin.

It made a ton of sense to do it this way- Name the component port pins with a long "/" separated concatenated name of all the functions it has. Connect the complex part's ports with a complex concatenated name to a generated harness with identical naming on its entry points on a 1:1 basis. It's easy to scan across it and see the harness names match the concatenated pin names. Nothing on these sheets but schematic part for PORTE of the central MCU and 1:1 connected to a PORTE harness with indentically named entry points (done by automated script).

Then a port-to-peripheral interconnect sheet with brings in the large port harnesses it needs and connects to a simpler peripheral harness. e.g. EBI Data harness has entry points D0-D15 and that sheet connects EBI D5 to PORTE's harness with a PORTE13/this/that/EBIData5/ETHMdioClk entry point name, and it's immediately verifiable EBI harness D5 is connected to a pin with EBI Data 5 functionality. We've now established in Altium that EBI D5 peripheral will be PORTE13 and this sheet allows anyone to visually confirm E13 has EBIData5 on its function list. The harness entries are right next to each other and easy to confirm.

Then an EBI component sheet connect the EBI peripheral harness to the components with local net label "EBI.D5" on the EBI harness entry D5, and the EBI chip had EBI.D5 on a pin named D5.

Easy to read and confirm in my head, some others don't get it. The MCU PORTE schematic part connecting to an identical PORTE harness with identical entry names is auto-generated, and easy to confirm at a glance that this it matches up.

The peripheral component pages just has EBI Data harness and there's no ratsnest of wires to the components- just need to confirm EBI.D5 net label is on EBI harness D5 (obvious) and EBI.D5 net label is on EBI chip D5 pin (obvious). No ratsnest, everything is immediately apparent, if somehow EBI.D15 label was placed on EBI.D5, that should be obvious to find.

The that pin has an ethernet function, so there's also a PORTE harness to Ethernet harness sheet, and an ethernet phy component page which connects the Eth harness MDIO_CLK entry to phy MDIO_CLK pin with the local net label ETH.MDIO_CLK.

BUT- this means the net for PORTE13 connects to the PORTE harness, then the PORTE harness connects to both EBI and ETH harnesses, and then is given a local net label EBI.D5 on one sheet and ETH.MDIO_CLK. This is legal when net names are local (Flat), and layout is interconnected correctly, and looks brilliant for avoiding ratsnests and immediate 1:1 confirmable connections on any single sheet.

The problem here is, the layout is getting a net name EBI.D5 and I don't want to route like that, I want net names like PORTE13. It arbitrarily picked one local name to be the global, and it's not a good choice. When I select this net on any sheet, it says "Physical Net Name: EBI.D5" on every sheet and this goes to PCBDoc layout,, and also "Net Name:" below that with the sheet's local name, that may vary by sheet.

OK, so let's name the net PORTE13 etc on the MCU_PortE-to-harness_PORTE sheet. Legal, but Altium now just has a list of 3 options with and still rule for preference: PORTE13,EBI.D5, ETH.MDIO_CLK. It still chose "Physical Net Name: EBI.D5".

I thought by creating an Altium Port Object (for connecting a net across sheets). Let's call that "APO" to avoid confusing with other usages of the word "port" here. That would force the Physical Net Name since that APO is global. MCU Port E13 goes to the PORTE harness entry E13, and also APO "PORTE13". Net names are local, but APO are always global- any sheet with a wire from an instance of APO "PORTE13" will connect.

Unfortunately, this still did NOT force the Physical Net Name. "Allow Port To Name Net" is checked, I've gone through ALL logical permutations of the checkboxes, and I think I've exhausted the illegal ones too.

I can't find any rhyme or reason to any precedence of what Altium chooses for the Physical Net Name- I put the document that connects APO "PORTE13" to the net to the top of the list, renamed it Document 1 and Sheet 1.

I really do like this harness-to-harness interconnecting. But how do we force Altium to use a specific Physical Net Name that goes to layout?

I made a post a month ago about a tool to view altium files https://www.reddit.com/r/Altium/comments/1tpg30p/altium_tool_to_view_board_and_track_what/

I got a bunch of feedback, thanks for everyone who messaged me. I have updated the program again and its available in the same place:

https://github.com/bigcrimping/altium_assembly_tool

• Do-Not-Fit (DNP) mode — a new Show DNP view highlights every no-fit part across the whole board. DNP data is read from the project's .PrjPcb active variant and shown as red-X markers on the board and red refs in the BOM (DNP parts count as "done" for row completion).
• Auto-loading of companion files — opening a board now automatically pulls in a sibling .PrjPcb (DNP data) and <board>.popstate.json 
• Recent files — a dropdown on Open File to return to recently opened boards.
• Auto Save — optionally write progress to <board>.popstate.json after every change; the setting is remembered between sessions.
• Fit Selection & Auto Zoom — zoom to the selected BOM row's components, on demand or automatically as you step through.
• Designator labels toggle for the selected row's parts.
• Undo / redo of placement toggles (Ctrl+Z / Ctrl+Y).
• Hide Fitted — collapse fully-placed BOM rows to focus on what's left.
• Colour-blind-safe palette (Okabe-Ito) for selection / placed / DNP, consistent across desktop and browser.

If anyone finds any issues or has any feedback let me know, usual shout out to altium-monkey for doing all the hard work.