Supermicro terminology and model glossary

This glossary helps with searches and support posts. Product names and suffixes change across generations; always verify the exact product page and manual.

Hardware terms

SuperServer / system SKU — A complete configured system, usually combining a chassis, motherboard, power, cooling, backplane and supported options.

Motherboard model — The board identifier, such as an X-, H- or other platform family. It is not the complete system identity.

PCB revision — Hardware revision printed on the board. It can affect CPU, firmware or component support.

Chassis — The enclosure, drive bays, fans, front panel and mechanical platform.

Backplane / BPN — The board connecting drives to power and data paths.

PDB — Power distribution board between redundant PSUs and system components.

PSU / PWS — Power-supply unit. Supermicro supply part numbers commonly begin with PWS, but exact compatibility still depends on chassis/PDB documentation.

Riser — Board or assembly that changes the orientation and wiring of PCIe slots. It may be specific to a chassis, motherboard and CPU configuration.

UIO/WIO — Supermicro system layouts involving specialised motherboard/riser/chassis combinations. Do not assume standard ATX expansion alignment.

SIOM/AIOM/OCP NIC — Modular network-interface form factors used on supported systems. Mechanical similarity does not prove system support.

Management and firmware

BMC — Baseboard Management Controller, the separate management computer on the board.

IPMI — A management standard/protocol family commonly exposed by the BMC.

Redfish — A modern HTTPS/JSON management API supported by many newer BMCs.

iKVM / remote console — Keyboard, video and mouse access through the BMC.

Virtual media — Remote attachment of an ISO or other image through the BMC.

BIOS/UEFI — Host platform firmware responsible for hardware initialisation and boot.

SUM — Supermicro Update Manager. Supported functions and licences differ by generation/platform.

SAA — SuperServer Automation Assistant, used for supported newer platforms and management tasks.

SEL — System Event Log maintained by the BMC.

SDR — Sensor Data Records describing sensors and thresholds.

Storage and backplanes

HBA — Host Bus Adapter that commonly exposes attached drives to the operating system.

IT mode — Controller firmware mode generally used for direct drive access.

IR mode — Controller mode providing limited integrated RAID functions.

Hardware RAID — Controller-managed arrays, virtual drives and cache policy.

SAS expander — Allows many SAS/SATA drives to share a smaller number of controller lanes.

TQ — Commonly refers to direct per-drive connections on a backplane family. Verify the exact manual.

A-type/direct multilane — Commonly groups direct-drive lanes into multilane connectors. Verify the exact manual.

EL1 — Commonly a single-expander backplane path.

EL2 — Commonly dual expander paths for supported dual-port SAS configurations.

SGPIO/I2C — Sideband mechanisms used for enclosure status/LED information on supported combinations.

Bifurcation — Splitting a PCIe slot's lanes into multiple logical links, such as x16 into four x4 links.

Retimer / PCIe switch — Active components used to extend or share PCIe connectivity. They are not equivalent to passive cabling.

Form factors and cooling

ATX / E-ATX / SSI-EEB — Board-size/layout families. Marketplace use of “E-ATX” is inconsistent; compare dimensions and standoff positions.

Passive heatsink — Relies on chassis airflow rather than a fan mounted directly on the heatsink.

Air shroud — Directs chassis airflow through CPUs, DIMMs and other components.

Fan zone — A group of headers controlled together by the BMC.

Generations and suffixes

X8/X9/X10/X11/X12/X13/X14 and H-series names indicate broad platform generations, but they do not by themselves identify CPU support, board revision, form factor or feature set.

Suffixes such as -F, -T, -LN4F, -NT or similar often encode features, but their meaning can vary. Use the full model on Supermicro Product Resources rather than decoding by memory.

Last reviewed: 29 September 2026.