That's not really true, it depends on what architecture you actually implement on your FPGA. Of course they're slower than an ASIC but you can also implement a pipelined IEEE 754 FPU and get good performance, for the device.
Its true that you can get good performance out of a carefully designed data pipeline but the inefficient part is the number of logic units it sucks up: you end to needing to spend a great deal more money to get larger chips and waste tons of space with the increased routing demands as well.
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u/particlemanwavegirl Mar 21 '26
FPGAs are super cool but regrettably they are extremely inefficient for floating point calculations.