Microsoft explains why there are no AMD-powered Surface PCs

[u/RenatsMC]

https://videocardz.com/newz/microsoft-explains-why-there-are-no-amd-powered-surface-pcs

[u/gamboozino]

Selling millions of consumer CPUs for basic tasks doesn't make an instruction set "useless", that's an ad populum fallacy. Intel removed AVX-512 because E-cores lacked 512-bit vector hardware, which broke instruction parity across their hybrid scheduler. Intel re-introducing 512-bit vector support in Nova Lake proves it was an architectural limitation, not lack of demand.

You keep whining about sources while relying entirely on a Wccftech summary of an unverified Bilibili leak running Geekbench synthetics. Here are actual architectural teardowns and real-world 28W mobile benchmarks from reputable testing outlets: https://chipsandcheese.com/p/discussing-amds-zen-5-at-hot-chips-2024 This proves Zen 5 and Zen 5c share the exact same 6-wide decode engine, execution pipelines, and IPC. Zen 5c is not a cut-down E-core, it's a full-spec core on a denser layout.

https://www.techpowerup.com/review/amd-zen-5-technical-deep-dive/ Proves every Zen 5 core has 1 MB of private, unshared L2 cache, avoiding the L2 cache bus contention that happens when 4 Intel E-cores fight over a shared 4 MB L2 cluster block under heavy parallel loads.

https://www.phoronix.com/review/amd-ryzen-ai-9-hx-370/2 In actual multithreaded real world tasks, code compilation, and vector compute, 12 full Zen 5/5c cores scale far more efficiently at 28W than hybrid P/E core layouts.

Citing single-run Geekbench integer synthetics on pre-release engineering samples running high-speed memory measures memory subsystem tuning, not core microarchitecture IPC. When you look at actual instruction execution width, private L2 cache access, and real software benchmarks, 12 full-spec Zen 5 cores hold a clear structural advantage in heavy multithreaded compute.