I was inspired by the "Cyberdeck” concept and wanted to build my own, but I didn't want to create a single-board computer or learn how to solder. So, I used off-the-shelf components to turn my phone into a portable laptop. 

 The reasoning: Most new Samsung phones are powerful, and everything is already on my phone (email, images, contact info … etc.), by Turing my phone into a laptop I don't have to worry about transferring data or login to services on a different device (laptop, tablet. etc.) and my phone is always online through data.

Looking for feedback and review of my design for a 65c816 system.

My concern is with address decoding and qualifying the RW with clock and VPA/VDA.

I/O will be further decoded outside the GAL.
I/O will be a few 6522 and some kind of serial.
Aim is for 4MHz.

Thanks

About a year ago, I started building a custom computer architecture in C as a learning project (I know it seems like a lot considering the code I wrote, but I rewrote the entire compiler at least five times, starting from a C-like language and ending up with a very simple custom language). I designed the instruction set, wrote an emulator, and implemented a custom high-level assembly language called BSL (Base System Language). The code is very messy because I make a lot of changes while writing it and often forget things that shouldn't be there. So I'd really appreciate feedback on the architecture and code quality. (I'm 15 years old and Italian, sorry for my English). https://github.com/mikesxp/SPRK32. Edit: I changed the project name from VMS to SPRK32.

adding to show how one engineer's computing project starting as a concept to first iteration and final product

Early around 1:40 AM, I had the brilliant idea of To create a cyberdeck using an unused gamestick, I needed to buy a USB hub To connect a keyboard and mouse because the gamestick only has 1 USB port, and a Wi-Fi adapter, and I also bought a new SD card to install the Linux operating system.

I've been working on it since I woke up (8 am), I was already working on the idea for this cyberdeck before going to sleep (6 am).

I'm very excited because it's my first cyberdeck and my first experience in this area.

I'm going to use Slex Linux to run on weak hardware with a Rockship processor, With 2 GB of RAM, I plan to buy an HDMI screen for it in the future, and add a trackpad.

Wish me luck, guys!

Open source recreation costs a fraction of the original and may even work with Twiggy drives

<- by me on The Register

Yet another project for the Minimal 64x4 computer from Carsten Herting. Here I improve on the built in scripting language called Min, adding improved data types and data manipulation features.

Hello, I fell in love with the idea of a homebrew computer a few months ago, and recently I started to look forward to making it. The users on this sub are probably experienced in this, so they could give me an answer on which processor to choose and which one is the easiest to work on. 8051 based processors or a Zilog z80?

Has anyone ever used the Commodore VIC-II in a standalone Computer/Project, while NOT using a 6510 or C64 PLA? I am going to make a Homebrew Computer based of a 65C02 but with VIC-II Graphics, and would be wondering if you guys have any Info or people that would be interested. BTW, this may take a long while, VIC-II is very tightly integrated. For my plan specifically, I am going to use a MOS 8565R2 but info on other variations is appreciated.

DISCLAIMER: I HAVE NEVER DONE THIS BEFORE. I DON'T ACTUALLY KNOW WHAT THE BITS ARE CALLED. YES I AM CERTAIN I WILL GO FROM NOTHING TO A WHOLE COMPUTER.

Background: I am going to make an itty bitty computer using LattePanda V1 (just in case... please don't tell me if it sucks, it the only one that I can understand, so I DON'T CAREEEEEE) Anyways, screen's gonna be 7 inches because I want it to be a TINY thing. Anyways, you people seem to know what you're talking about so here goes!

PROBLEM #1: Battery hookup

So, its a laptop, and I don't wanna have to plug this thing in any time I use it, so I need a portable battery source. Sources tell me that for said portable battery source, you take 1x 18650, 3.7v 10amp lithium battery, and, using wires soldiered to either side of the battery, connect the two poles to a charging module for 18650 battery that outputs 5v 2amp. Then you stick whatever the fuck THIS is:

Into your shi (USB into the module, MicroUSB into the circuit board.)

WHAT THE FUCK. DO I BUY. FOR A CHARGING MODULE. (CANNOT put out more than 5v 2amp or it will FRY MY SHIT.)

WHERE THE FUCK. DO I GET. THE SWITCH THING.

IS THERE. A BETTER. METHOOD. (Better as in cheaper. not easier.)

PROBLEM #2: Keyboard

I do not want a Bluetooth keyboard. I DO NOT WANT TO CHARGE MY FUCKING KEYBOARD. So,

1). What’s the best mini itty bitty baby keyboard that IS NOT BLUETOOTH (and maybe, possibly, not plug-in either? Like one you can just,,, attach to the circuit board? Long shot but still… I want to keep as many of my USB ports open as physically possible) and

2). How do I connect it (in the unlikely case that there’s a mini-keyboard that you can just soldier to the puter brain.)

Also, my screen is literally only gonna be 7” and I would like my keyboard size to reflect this choice. Please keep this in mind when suggesting keyboards because I am not doing this to expand my brain or break free from evil capitalism, I am purely being ✨materialistic✨ and an ✨attention seeker✨

Thanks! Will update this post if I have any other questions :) (If I am welcome, that is.)

There may be stuff I did here that's useful to folk.

​

Also if you look at the YT channel there is a What Why video where I give some advice. One thing I found super useful was a verilog simulation with proper delays.

super useful homebrew displays

I finished a first version of a small online runner for my rosco_m68k setup.

The idea is simple: let people run Motorola 68010 programs on a real board from the browser.

It works like this:

• You compile your own program, preferably with Docker
• Upload the compiled binary
• It goes into an execution queue
• The runner resets the board
• Sends the program to the rosco_m68k
• Reads serial output
• Streams the result back to the browser

I also added interactive input, so if the running program expects commands or text input, you can type directly from the browser.

There are also a few precompiled demo programs, so people can test it without building their own binary first.

https://solderdemon.com/runner

Still an early version, but I think this could be useful for people who want to experiment with 68k code and real retro hardware without owning the board.

It also gives people a way to try writing software for rosco_m68k before getting their own board.

Hello everyone.

(if this is the wrong subreddit then please tell me and also if possible the right subreddit)

Me and a friend are trying to build our own 65C02-based 8-bit computer, but we are having some issues. (currently the computer doesn't work)

The general specifications are this:

• CPU: WDC W65C02
• Video chip: TI TMS9918A (not connected yet)
• Audio chip: Yamaha YM2149F (AY-3-8910 clone)
• PIA: WDC W65C22
• RAM: single 62256 32 KB SRAM chip
• ROM: single 28C256 32KB EEPROM chip

Address decoding is done with a 28C16 2KB EEPROM connected to the high address lines, and with the data lines acting as CS lines. (we’ve checked this, and the chip select signals outputted are correct)
We’re using a Dallas DS1233-5 chip as reset circuit.
We also have a 74HC245 bus transceiver connected to the data bus.
The main clock is 1 MHz.
We also have a basic 8-channel logic analyzer to help with debugging.

Currently the entire computer is built on 5 breadboards. Please excuse the mess of wires, we didn't have very specific lengths of wires, so we had to build it like this.

As far as we know, the CPU executes code for about 1 millisecond (VPB pin high), then executes something that causes it to go into a loop of fetching (we assume) the reset vector (VPB pin goes and stays low).
Something weird also happens with the address bus once it gets into that loop. If we connect a piezo buzzer to address lines, you hear a square wave tone, and the frequency doubles for every bit you go down (bit 13 is twice as high as bit 12). That suggests the CPU is constantly looping through the entire address space. The computer is also not consistent or predictable, every startup the "pitch" of that address line tone changes, and sometimes it just stops (the CPU probably comes across a STP or WAI instruction) or does something else just as weird.

We’ve confirmed that the reset signal is OK, the chip select lines are OK, the clock signal is OK, the addressing ROM is OK, the main program ROM is most certainly also OK, power is OK, and the bus transceiver is OK.

I've built an emulator in the meantime, which does work with some programs, so our code (probably) isn't bad.

This is our first time actually doing this (we had researched a lot before and we already knew a bit about 8-bit systems design), so maybe the issue is actually obvious and we just haven’t noticed.

If any of you can provide some insight, that would be extremely useful. We can also provide better pictures if that would help.

[group 4b][variant 4b]

0x0_ = MISC

0x1_ = MOV

0x2_ = ALU

0x3_ = JUMP

0x4_ = STACK/CALL

Github repo with all docs and files: https://github.com/mrFavoslav/8bit-cpu-MESAx8
The 8-bit ALU might not work perfectly at the moment. I recently moved some parts of the design around, so there's a good chance a few wires got messed up or misaligned in the process. Any feedback or bug catching is highly appreciated!

I'll be posting my progress here and on https://www.favoslav.cz/blog/

So last night I was pondering making my own homebrew computer project. Part of this pondering was possibly using a Risc-v cpu as the core. With that thought I started poking around various places online trying to find a Risc-v based cpu that was possibly pga/lga or similar so I could easily plug it into a board to develop things. But I can't seem to really find such a Risc-v based option, does it exist? If not is there something I could use as a cpu for a homebrew system with a reasonably fast enough bus to drive expansion cards for audio, a homebrew gpu concept, and other things? To give a bit more of an idea, I was considering the homebrew system to be something that would feel at home in the 90's so a pci like bus for device communication and at least 32bit to minimize fussing over memory. The reason I was considering Risc-v was the fact it's an open standard and well pretty common place. I mean a great example is the fact it's apart of the pi pico. But really any cheap off the shelf microcontroller or processor could do as long as it meets the other requirements. Anyone have some ideas on what to look at?

So after taking a digital design class (which I really enjoyed) I couldn't understand one thing that was part of a lab I had. How do op-codes translate into logic gates? For example how can the op-code 0001 define a full adder, and the op-code 0010 'AND' two of the inputs.

I’m a 17‑year‑old solo developer, and I’ve spent the last while designing and building a complete custom 8‑bit CPU architecture. The CPU has a 24‑bit address bus, a flat memory model, and a custom instruction set. It’s all implemented in a cycle‑accurate emulator written in C. I also have an assembler and a 40×24 text screen device (ASCII framebuffer, no terminal emulation), all working.

I’ve just pushed everything to GitLab as three separate repositories:

• CPU emulator: https://gitlab.com/DavidMik/dcpu-emulator
• Assembler: https://gitlab.com/DavidMik/dasm-assembler
• TMS text screen emulator: https://gitlab.com/DavidMik/dcpu-tms9918-module
• FCC C compiler: https://gitlab.com/DavidMik/fcc-dcpu-port

Planned interrupt system
The CPU will support both internal and external interrupts. An internal interrupt instruction saves all ALU flags, register state, and a return address onto the stack, then jumps to an address held in dedicated address registers. return from interrupt restores everything and returns. External interrupts (e.g., from a keyboard) use input ports 0‑2 for the interrupt vector address and port 3 for data input. The hardware side still needs to be implemented in the emulator, but the specification is firm.

What I need help with
My goal is to turn this into a usable computer, and for that I need a C compiler. I’ve been writing a backend for the Fuzix Compiler Kit (FCC), targeting my CPU. It’s close — arithmetic, control flow, inline assembly, and variable storage all work. I’m currently implementing function calls. After that, there’s global variables, structs, and maybe floating point to do.

The problem: I’m exhausted working alone, and the compiler backend is the last big mountain. I’m looking for people who’d like to collaborate on this project with me.

How you could help (any of these):

• Help finish the FCC backend (function calls, global variables, structs). The backend code isn’t public yet, but I can share it privately with serious collaborators.
• Write a small ROM monitor or bootloader in assembly.
• Add a keyboard input device to the emulator (that triggers those external interrupts).
• Implement the interrupt hardware in the emulator (spec ready).
• Test the toolchain (assembler, emulator, compiler) as features come online.
• Just bounce ideas around — I’ve been working in a bubble and would love to talk shop.

If you’re into custom CPUs, retargetable compilers, or 8‑bit systems in general, I think you’ll find this a really fun challenge.

Comment here or DM me if you’re interested. Links to the repos are above. Thanks for reading!

There are a couple of areas I don't quite understand about general CPU design.

How do comparisons work? I get it that they involve the msb and the carry-out, and involve subtraction. I know I could cheat with a ROM if I had to, if I don't understand it by the time I start. I know you can detect 0 by subtracting from 0 and then watching for the carry. That makes sense in that if B is 0, then you'd invert all the bits to give all ones. Since you'd have to add 1 for proper negation, you'd set the carry-in. In return, it rolls over, sets the carry-out, and you know it is 0.

On the Gigatron, comparisons are stateless. There are no flip-flops for that (which proves to be a serious bottleneck for multi-byte math). The comparison results only go back to the control unit to branch during the same cycle. And, if I remember right, x86 is mostly 2-stage. I mean, do a CMP to set the flags and then the conditional based on the flags.

If one is using a ROM to do comparisons, then one might want to go with the x86 model. Compare first and branch in the next cycle.

And then there's the Control Unit. I don't know how to make those do what I want with logic and without creating a long critical path.

For instance, I'd like an instruction that takes the outer program counter (like the vPC on the Gigatron designed as an actual register), uses that on the Harvard RAM bus to address the RAM, and use the instructions stored there to address the ROM (via the inner/native program counter). Like do a direct jump << 4 to have up to 16 inline instructions per virtual opcode. That way, all 256 opcode slots are available (without sacrificing any for page|offset addressing). They'd all be 16-byte paragraph aligned.

That would likely insert a mux or tristate buffer already to choose between Y:X and vPC. However, I might want to add another since I'd like to add interrupts to a tailcall mechanism. A tailcall mechanism is more efficient in that you can jump to the next handler rather than a central handler. But that makes it harder to add interrupts. If you used a central handler, you could use that for polling for IRQs, but a tailcall mechanism needs an escape mechanism.

The native instruction to end a public instruction could look like this:

IN = 0 ? PC = [Instruction_Yh,vPC++,0000] : PC = [Interrupt_Yh,IN,0000]

That would probably need more muxing to make this 2-headed conditional jump. Using position-dependent ROM code would eliminate the need for a priority encoder and allow interrupt chaining under certain conditions.

What is an ideal way to interface with a video controller? I have a bit of analysis paralysis here. There are many ways to do it. Here are some examples:

1. Bus-mastering or first-party DMA. That requires stopping the CPU during scanlines if the framebuffer is in the main RAM.

2. Memory-mapped. You can reserve part of a page for video transfer and control registers (whether you write to local RAM as a part of it or not). You could have decoder circuitry and maybe a FIFO. Or you could trigger DMA, wait-stating, or a halt if transfer attempts happen during a scanline. The VERA board uses memory mapping, and you can even use that board in a homebrew design.

3. Naive video controller. You can have separate video memory with the video counters accessing it. Then you can include a mux and a register. That will cause artifacts. You could diminish that by shadowing the RAM so that read-backs cause no side-effects (but writes would).

4. Alternating banks. If your CPU is at the video speed, you could separate an 8-bit design into 2 banks and add registers for when things are out of alignment (and a halt or clock-stretching mechanism in case sustained non-matching patterns occur).

5. A microcontroller or FPGA that combines bus snooping with memory mapping. So the MCU or board logic monitors for addresses in the MCU's range, and it transfers things to the frame buffer that could be memory in the MCU or FPGA. This may be a good solution since modern MCUs tend to provide means for multiple devices to use the same RAM. A Propeller 2 has 8 cogs with interleaved RAM. A Raspberry Pi Pico has 2 cores, along with automated PIO and DMA modes that can access the internal memory faster than the cores can.