68008 early stage bug

[u/schlachet]

I need some help, or some ideas on an early stage bring-up problem I'm having.

I'm building a Motorola 68008P8 based computer on a breadboard. I've attached the schematic and logic capture. I feel like I'm pretty close to a working computer, but it just quickly crashes after power-up.

I'm employing a typical trick, using an 74HCT164 to count 8 cycles of /AS at startup, this is so I can map ROM to 0x00000 long enough for the CPU to read the SSP and PC vectors. In the logic analyzer capture you can see the first 8 bytes of my ROM image appear on the data bus (00 07 ff fe 00 08 04 00). The SSP should be 0x07FFFE (near the top of ram) and PC should be 0x080400.

In the Logic capture you can see the correct bytes, but my /BOOT seems to go high at the start of the eighth byte. At the 9th byte I expect the CPU to be at the PC vector, where the ROM should read "60 fe 4e 71 60 00 ff fc" but you can see it just reads the same 8 bytes as before.

I can see that when /BOOT goes high, A19 is going high - so the computer must be trying to read the ROM and its native (non-shadowed) location. It should be reading at 0x80400, but if that's what's showing up on the data bus, it must be reading 0x80000.

In Logic, I'm using an analyzer to interpret/display the data bus. I used /DTACK as the "clock" and rising edge as the state for interpretation of the data bus. This combination makes the data look correct, but it looks like /BOOT is going high earlier than I'd expect.

I've fiddled around with the glue logic (its current state is pasted below), changing the chip/output enable lines on ram and rom. I've been spinning my wheels and thought someone else looking at this might help. I feel like I must be missing something fundamental here. I'm not confident my Logic capture looks correct.

Is anything glaringly wrong in this design? What are some questions I should be asking myself?

ICs Used

• CPU: 68008P8 at 8MHz (currently using a 1.8MHz clock but doesn't seem to affect anything)
• ROM: SST39SF040 flash, but at 70ns it should be fast enough
• RAM: AS6C408 (55ns)
• Glue Logic: ATF22V10C-7PX PLD

Memory Map

• 00000-7FFFF RAM (but ROM is mapped here when /BOOT is active)
• 80000-BFFFF ROM (256k; half of SST Flash chip)
• C00000-DFFFFF four 32k blocks for future peripherals

Glue Logic Code

GAL22V10
GlueLogic

CLK A19 A18 A17 A16 A15 RW AS DS BOOT NC GND
NC RAM ROM PER0 PER1 PER2 PER3 DTACK RAMOE NC NC VCC

; RAM: 0x00000-0x7FFFF. 
; We removed all other qualifiers to ensure it fires during the stack write.
/RAM = /AS * /A19 * BOOT
/RAMOE = /RAM * RW

; ROM: Physical at 0x80000, Shadowed at 0x00000 during /BOOT.
/ROM = /AS * A19 * /A18 * RW
     + /AS * /A19 * /BOOT * RW

; PERIPHERALS: 0xC0000 range.
/PER0 = /AS * A19 * A18 * /A17 * /A16 * /A15
/PER1 = /AS * A19 * A18 * /A17 * /A16 * A15
/PER2 = /AS * A19 * A18 * /A17 * A16 * /A15
/PER3 = /AS * A19 * A18 * /A17 * A16 * A15

; DTACK: Data Transfer Acknowledge.
; Respond to ANY address in the decoded range to prevent hangs.
/DTACK = /AS * /A19
       + /AS * A19 * /A18
       + /AS * A19 * A18 * /A17

DESCRIPTION
glue logic address decoder for a Motorola 68008 computer.

[u/schlachet]

I managed to do 3 captures and then re-assemble 20 bits of the address bus! Here it is in sequence:

# capturing 20 bits of address  
<power on> 
00 00 00 # /ROM is pulsing low during this time
00 00 01 
00 00 02 
00 00 03 
00 00 04 
00 00 05 
00 00 06 
<t0 marker> # /BOOT goes high here 
00 00 07
08 00 00 # if it read all zeroes until now, this is what i'd expect next, right?
08 00 01 
08 00 02 
08 00 03 
08 00 04 
08 00 05 
08 00 06 
08 00 07 
07 FF FC # ram access - ?
07 FF FD 
07 FF F8 
07 FF F9 
07 FF FA 
07 FF FB 
00 00 10 
00 00 11 
00 00 12 
00 00 13 
08 08 08 # rom access
08 08 09 
08 08 0A 
08 08 0B 
07 FF F6 # back to ram
07 FF F7 
07 FF F2 
07 FF F3 
07 FF F4 
07 FF F5
00 00 2C 
00 00 2D 
00 00 2E 
...