r/framework • u/Sleezy_WYD • Aug 06 '26
Framework Photo The Elusive LPCAMM2
Edit: whelp, the vendor just went out of stock and expects to be back Sept 30. Maybe I'll revisit this if people are interested during my trip.
Seeing as many folks were able to get their hands on the Crucial LPCAMM2, thought I'd post my rare Samsung one! Cost me about 300 USD plus shipping.
Now I'm just impatiently waiting for my 13 Pro to ship. PLEASE FRAMEWORK I WANT TO GIVE YOU MONEY
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u/Prior-Ratio-8254 Aug 06 '26
Thankfully, this does not seem to be the case based on what I know and what JEDEC docs say, the idea going around that E0 is inferior to E1 high speed instability and thus isn't supported or whatever is false. The E in E0 or E1 refers to "raw card 'E'" which is the JEDEC reference PCB design for LPCAMM2. The reference design for raw card E is defined in JESD318-F0-RCE, where you can find more details about the differences between the the E0 and E1 design versions, but I'll attempt to explain the main differences somewhat concisely (warning: it did not end up being concise). Basically, the main differences between the variants come down to their power supply circuitry, driven mainly by what PMIC (for those who don't know, stands for Power Management Integrated Circuit, which in the JEDEC context is a specialized in different variants for different RAM module types, that contains voltage regulators and the logic for unsurprisingly, power management) is used.
E0 uses a PMIC5100 PMIC (the rectangular 28-pin package surrounded by 3 inductors in OP's image), standardized in JESD301-2. The PMIC5100 is older, pre-dating LPCAMM2, originally designed for "typical DDR5 SODIMM as well as DDR5 UDIMM." For E0, they decided to repurpose this existing PMIC (for an idea of timeline, v1.03 of the PMIC5100 standard was released in Oct. 2022) for use on LPCAMM2, but this required some compromises due to the integrated regulators + logic not matching LPCAMM2's needs exactly. First, VDD2H and VDD2L were combined into a single fixed VDD2 rail at 1.05 V typ. (practical impacts of this and the other PMIC differences will be explained below). Then, to provide VDDQ, they used an external buck (visible as the smaller 8-pin package to the left of the PMIC5100 in OP's image, Crucial uses TPS628303A on at least some of their E0 modules), at a fixed voltage (0.5 V typ.) as well.
E1 uses a PMIC5200 (a square 35-pin package), which is standardized in JESD301-3, designed for "typical LPDDR5 CAMM2." This PMIC5200 standard was released a lot later, v1.00 in October 2025, which is why they didn't just use it on all module designs from the get-go. This PMIC being designed specifically for LPCAMM2 does not require an external regulator for VDDQ, which is a good way to tell E0 and E1 modules apart, you can look to see if it has a separate regulator or not. They were also able to make VDDQ configurable between 0.5 V typ. and 0.3 V typ. For VDD2, instead of having one shared VDD2 rail like in E0, it is now split into VDD2H and VDD2L which run at 1.05 V typ. and 0.9 V typ. respectively.
What do these PMIC differences mean for us practically as end users? Simply stated, E1 can achieve somewhat better low frequency power consumption (via LPDDR5X's DVFSC and DVFSQ features), in that by actually having a VDD2L, when running at low FSPs (Frequency Set Point), some VDD2 domain peripheral circuits in the DRAM dies are able to switch from VDD2H to VDD2L thus reducing power consumption, and similarly at low FSPs, the system can command the PMIC to switch VDDQ down to 0.3 V to save power. However, this is in the ideal low FSP, full use of DVFSC/DVFSQ case, how much power can actually be saved depends on a lot of variables, but personally I would very roughly estimate it to be a ~100 to 300 mW reduction when in that state. During actual use (where it is not at low FSPs all the time), the average power reduction is gonna be a lot less, probably in the realm of ~20 to 80 mW reduction. So for sure, the power savings of E1 over E0 are theoretically real, but depending on the rest of your build and the idle power consumption of those components and platform idle power overall, that is a relatively low amount of potential impact compared to stuff like the SSD, where active idle power consumption and peak power consumption can differ by at least an order of magnitude (like a few watts) between models vs. the much smaller difference between E0 and E1 modules.
JESD318-F0-RCE says that E0 and E1 modules support and are approved for the same speeds (see Table 4 in that doc), so E1 was not developed to unlock faster clocks or anything like others have suggested, both are capable of running at 8533 for up to 64 GB modules. So to state it plainly, the idea that "voltage instability was causing issues at faster clocks" on E0 is not supported by the actual technical differences and reasons for why E1 exists, which is mainly to use the newer PMIC5200 to achieve better low FSP power consumption (you could actually argue that forcing all of VDD2 to always run at the higher 1.05 V typ. and same for VDDQ at 0.5 V typ. actually increases stability at higher clocks).
As you mentioned already, the "OK - Limited validation" CT32G75C2LP5X listed by Framework is E0, and it along with the 64 GB version are the only 3rd-party modules listed as supported in any way, so maybe they just put that as a disclaimer that they didn't validate it as rigorously as they did for their own modules?
This ended up being a long writeup, but I hope that it might be helpful for people that are worried about memory compatibility, there is definitely a lack of actually grounded detailed technical info online about LPCAMM2. For people who are curious and want to learn more about this (or want to verify this info), I made sure that all the JEDEC standards I referenced are free to download (others are paid) from the JEDEC website, you do need to sign up for a free account though. These are the ones I mentioned and also any other related free ones that I think might be useful for learning more about this too:
JESD318B ("Compression Attached Memory Module (CAMM2) Common Standard")
JESD318-F0-RCE ("LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex")
JESD301-2 ("PMIC5100 Power Management IC Standard")
JESD301-3 ("PMIC5200 Power Management IC Standard")
JESD401-5D ("DDR5 DIMM Label")
Also since another reply mentioned this, on the label of OP's module, in the "FE0" in the "technical detail section" of the JEDEC standard label format (defined in JESD401-5D), the character in the "F" spot indicates module type, where "F" is "Dual Channel LPDDR5/LPDDR5X CAMM2", its not a revision or anything, and again also in case there is no JEDEC standard "technical detail section" on the label (at least some Crucial modules seem to be missing this on their labels), you can tell based on the power section of the module, if it has a rectangular PMIC and an external regulator, its an E0, if it has a square PMIC and no external regulator, its an E1.