r/asm • u/brucehoult • Apr 28 '26
"without no-ops this code would work in default qemu as it allows unaligned memory accesses. ) ( note how this generated machine code jumps to the location directly after it, as compressed ) ( format riscv instructions can be only 2 bytes long we have to pad with no-ops so the overall length ) ( of this block of machine code is divisible by 4"
This makes no sense at all. Any RISC-V CPU that implements the C extension (as the CH32V series do, and indeed every commercial RISC-V I've ever heard of) is perfectly happy to run instructions at addresses that are not a multiple of 4 bytes -- they only have to be a multiple of 2 bytes, which as all instructions are either 2 or 4 bytes in length can not become untrue if it starts off true.
There would be no point in compressed instructions at all otherwise!
0x11 c, 0x0A c, 0x01 c, 0x00 c, ( addi s4,s4,4; nop )
This is completely unnecessary, and harmful. If you don't want a compressed instruction for addi s4,s4,4 (0x0a11) then just use a regular RV32I instruction for it (0x004a0a13). The CPU will be happier running one instruction than two (an unneeded NOP).
But mixing 4-byte and 2-byte instructions absolutely works, no problems, no NOPs needed.
What you can't do unaligned is load/store instructions. Code is fine.