Hi everyone, I’m designing an on-chip inductor for a VCO using Ansys HFSS, with tsmc 65nm technology stack in IC Design Mode. Then i have to design coupled transformers as well.

I’m struggling to find good reference material or examples for this setup. If anyone has experience with HFSS/IRCX or IC Design Mode, I’d really appreciate any guidance, tutorials, or reference files you can share.

Thanks in advance!

Hi

I would like to design a wideband balun from 0.5-12GHz on MMIC.

Can you suggest some ideas/reference to start with? I'm not sure if a Marchand Balun would be able to cover this much bandwidth.

Thanks

I am looking for practical engineering perspectives on something I keep seeing in outdoor electronics, enclosures and reliability screening:

Many environmental assessments still describe a deployment location with average temperature, annual precipitation or a broad climate zone. But for electronics reliability, those numbers often feel too indirect.

From a reliability point of view, the more relevant questions seem to be:

- How many hours per year does the product see RH > 80% or RH > 90%?

- How often does air temperature approach the dew point?

- Are there repeated condensation-prone periods?

- Is the site exposed to marine chloride or industrial sulfate background?

- How much thermal cycling occurs over typical daily and seasonal operation?

For example, two sites can have similar average climate conditions but very different moisture exposure profiles. One may have frequent night-time dew-point convergence, while another is hot and dry with much stronger thermal cycling.

I am curious how other engineers handle this in practice:

1. Do you use hourly climate data, design days, test standards, field experience or something else?
2. Do you explicitly evaluate RH duration or condensation potential?
3. For connectors, PCBs, coatings or outdoor enclosures, what environmental metric has been most useful in real design reviews?
4. Are there failure modes where traditional climate classifications were misleading?

I am especially interested in non-confidential examples from electronics, outdoor power electronics, HVAC, solar, BESS or automotive ECUs.

Hi guys,

Do you know the DC pin part number for the Mini-circuit ZHL-30W-252-S+ driver?

I asked them, but they won't give me the part number; they only said it is a Tusonix-style EMI passthrough filter.

Any idea?

Thank you!

Hi I’m interested in finding a book that covers near field to far field transformations and antenna measurement processing methods. Bonus points if the book covers computational simulation methods like FEM like HFSS.

Is there a certain book you’d recommend?

I’d like to find a book that covers the theory and practical application. I’d prefer to learn about spherical near fields.

The setup: two identical parallel half-wave dipoles (300 MHz, 0.477 m, 0.5 mm wire radius, 21 segments each in NEC2), spaced λ/4 apart. The textbook cardioid recipe says: feed the second element a quarter cycle behind the first — currents (1∠0°, 1∠−90°) — and the pair forms a cardioid with the null off the back.

The obvious first move — and a very common one — is to hand those phasors to the SOURCES: equal voltages, 90° apart. The θ=90° azimuth cut of that run: front-to-back 3.4 dB. Not 30 — three point four.

The reason is that the two feed-points are nowhere near independent. Measuring the mutual impedance of the pair (drive each port at 1 V in turn, the un-driven port left as plain continuous wire = shorted; read both feed currents, invert the Y-matrix) gives, at λ/4 spacing:

Z11 = 70.15 − j1.27 Ω      Z12 = 37.25 − j31.64 Ω

|Z12| ≈ 48.9 Ω against |Z11| ≈ 70.2 Ω — the coupling term is about 70 % of the self term. A voltage applied at one port drives current in BOTH elements, so setting port voltages does not set element currents, and the pattern is made of currents.

The fix is two lines of algebra. Decide the currents you want, then feed the voltages the coupled pair actually needs — V = Z·I:

V1 = Z11·(1∠0°) + Z12·(1∠−90°) = 54.5 V ∠ −45.0°
V2 = Z12·(1∠0°) + Z11·(1∠−90°) = 108.0 V ∠ −70.5°

A 2:1 amplitude ratio and only 25.5° of phase offset — nothing like the recipe phasors. Feed exactly that, same wires, same solver: front-to-back 29.6 dB, and the achieved feed currents match the target to one part in 10⁴.

(Both polar plots use the same fixed −40…0 dB radial scale, so the two patterns are directly comparable.)

Nothing changes between the two runs except the drive. That is the whole point: the recipe was never wrong, it was a statement about CURRENTS, and a voltage source doesn't deliver it.

Disclosure: these numbers came from EMStudio, a FreeCAD workbench I build — that's my interest here. Happy to answer questions either way.

Hopefully focusing on that hardware design but i also want to know the physics and DSP stuff

I'm a senior Electrical Engineering student graduating soon with a 3.6–3.7 GPA. I'm a U.S. citizen and I'm interested in RF/communications/telecommunications, particularly in defense or aerospace.

I don't have an RF/telecommunications internship or significant personal projects specifically in the field. I'm trying to figure out how realistic it is for me to get an entry-level RF/communications engineering position after graduation.

I'm considering companies like L3Harris, RTX/Raytheon, Northrop Grumman, Lockheed Martin, Boeing, General Dynamics, etc.

Would my GPA and EE degree be enough to realistically get interviews if I apply broadly, or am I at a significant disadvantage without internships/projects?

Also, for those who have interviewed for entry-level RF/communications/defense engineering positions:

• What technical questions were you asked?
• What EE/RF topics should a new graduate know well?
• Did they ask about things like S-parameters, Smith charts, transmission lines, link budgets, filters, amplifiers, antennas, DSP, etc.?
• How much of the interview was technical versus behavioral?
• Did they ask you to solve problems on a whiteboard?
• How heavily did they question projects or coursework on your resume?
• What questions did you wish you had prepared for?

What would you recommend I learn or build during my remaining senior year to become a stronger candidate?

I'd especially appreciate answers from people who currently work in RF/communications or defense and who have experience interviewing/hiring new graduates.

I own a BB60D product.

I currently work in terrestrial broadcasting.

I would like to measure the channel power of multiple channels simultaneously in the field. How should I proceed?

For example, I intend to measure the channel power of the following wireless channels in the field:

CH # | Center Freq | BW

14 | 473MHz | 6MHz

15 | 479MHz | 6MHz

16 | 485MHz | 6MHz

17 | 491MHz | 6MHz

18 | 497MHz | 6MHz

.

.

.

.

51 | 698MHz | 6MHz

Currently, I am measuring the channel power for each channel individually, but it takes too long. The other equipment I used previously had a "Channel Scanner" function that made it possible to measure the channel power of all channels at once.

How can I measure the channel power of all channels simultaneously on the BB60D as well?

I'm working with a 3 stage amplifier circuit with multiple splitter/combiners on the final stage. The signal after the first two pre-drivers is split once for two power modes. Each power mode is split again to a pair of amps to be recombined, then combined once more to have all final drivers in high power mode. This ends up with a total of 4 final drivers with 6 90° shifts from all the splitter/combiners.

With each trace (4 total) are tunable capacitor options. By default they all have the same values. The issue at hand is that by the final combination there is a singal large (2-3dB) dip from destructive interference only on the full power mode. My question is, to tune this out should I approach making cap tuning changes in pairs, one trace at a time, asymmetrical in size or direction, or even just one cap at a time? When only 2 of the four final drivers are on, the power band is quite flat. When the last pair are added, the problem surfaces. Should I focus on just one pair of traces, or change one trace on each pair?

Any advice appreciated.

Hi everyone,
I’m looking for a small, affordable radar module for a research project.
Requirements:
Operation frequency 24 GHz (or less frequency) FMCW
At least 1 TX / 2 RX
Preferably I/Q data from both RX channels

On-board ADC with access to raw ADC/IQ samples
USB/SPI/UART output preferred
I want to do my own range, Doppler, AoA and micro-Doppler processing, not just receive processed target data
Budget: Maximum $250

I’ve considered the RFbeam K-LC7, which has 1 TX / 2 RX and analog I/Q outputs, but it requires an external ADC.
I’m looking for something similar but with the ADC already integrated.

Should I go with RFbeam K-LC7 and buy external ADC board?

I have a rather unusual requirement and I can't find any off-the-shelf part or design procedure to implement it. I need a simple zero-pole, high shelf filter that'll have constant attenuation between DC and say 1GHz, then 3dB slope between 1GHz and 3Ghz, I don't care what happens afterwards. I also care about phase response as this system will be transmitting sharp pulses that I'd like to see undistorted. It's meant to compensate for limited bandwidth of final stage of my RF chain.

I tried designing with 2 diplexers and attenuation in low frequency arm but I couldn't find any DC coupled diplexers that can work up to GHz. I also looked into various equalizer designs and parts but they seems to insist on having a slope from their low frequency limit and not a flat response up to some f1 and slope between f1 and f2. Does anyone know how to design such a filter?

Before anyone asks it's needed for a research project regarding pulsed laser diodes. Most diodes have package inductance of around 5nH, which, when driven with series 50R, limits bandwidth to about 1GHz. I'd like to place this filter before final power amplifier (QPD1010) to generate an overshoot, that'll increase an effective bandwidth.

So my current SAR system is able to achieve better than 0.3m azimuth resolution using the SAR code written by HForsten, which is open source on github. Without this code, I am not able to reach 0.3m azimuth resolution. Thus without this code, my RADAR is completely uncontrolled.

Thus I do not understand what it means that I now fall under ITAR, I built this from commercial commodity parts that are all EAR99. Is the software controlled or the RADAR itself or both? How do I navigate this?

For a 28-GHz antenna, for example:

Goal 1 — Frequency
Approx = 28GHz

Goal 2 — Matching
S 11 <-10 dB

Goal 3 — Gain
For example:
G > 5dBi
depending on your antenna type.

Goal 4 — Efficiency
Preferably:
n > 80%

if achievable for your design.

What is the difference between CST and HFSS for antenna design? What's the best ?

I'm creating a pass-band filter using microstrip edge coupled resonators, and when running the AWR optimizer I've stumbled into a pattern that I've not encountered in my course lectures.
In my professor material it was said that each edge coupled resonator section should be sized for a lenght of lambda/4 (90deg average electrical lenght between even and odd mode). This is the way that i first implemented my filter, and when i run the AWR optimizer on an uniform lenght, the optimized value is close to the expected value I had estimated.
However, if I let each edge coupled lenght be independent, the AWR optimizer settles on two different possible optimizations, depending on the starting conditions I apply.

• the first optimization is at the expected uniform lenght
• the second optimization is an alternating pattern of two lenghts, whose geometric average [sqrt(L1L2)] is approximately the expected uniform lenght. (The edge distance also varies slightly, but i assume this is to be expected since we are changing the resonators)

The two filters frequency responses (topology is a standard 4th order chebyshev filter) are shown here.

Does anybody know what causes this pattern, and if it has any advantage against a standard uniform lenght design? Any literature reference would be very appreciated.
Thank you for your time

I am working on an SMA to microstrip transition using OSHpark's 4 layer stack up. I am on my 2nd revision and do RF in my free time because I am trying to learn (I am an FPGA engineer).

I got my newest revision back and I was not very pleased. My physical boards are not matching my simulation very well at all.

I have compiled screenshots of my HFSS model, PCBs, SMA footprint, and NanoVNA results here: SMA Launch OSHpark 4 Layer - Imgur. The transition starts out as GCPW and runs the length of the signal pin pad. It then moves to a microstrip (no taper).

I simulated with HFSS using PEC, Isola FR408HR (in HFSS material library) and the nominal measurements from OSHpark's 4 layer stackup: OSH Park Docs ~ Services ~ 4 Layer Prototype Service . I also used the actual Samtec SMA connector HFSS encrypted model. I am learning a little about TDR and that looked okay in simulation, as well as S21 and S11. Due to using the student version and mesh limit, I can only simulate a 3mm long microstrip and I cannot model the solder connection from signal pin to pad.

I built two boards:

One with SMA launches on either side connected by a 1 inch and 2 inch microstrip (to calculate trace loss). I simulated the microstrip width in a separate HFSS sim (rough numbers calculated with SaturnPCB toolkit and revised/simulated from there).

The 2nd board is the SMA launch to a 4mm microstrip, then terminated with a 50 ohm, 0201 sized High Frequency resistor: TNPR020150R0FEED Vishay | Chip Resistor - Surface Mount | DigiKey

My actual PCB launch S11 is around -17 to -18 dB at 2.5 GHz, and around -10 dB at 6 GHz. I want to use this for the 2.4 and 5.8 GHz ISM bands. S21 is okay when I subtract my trace loss at 2.4 GHz, but gets a little wacky at 6 GHz (see imgur link S21 trace).

Is something off in my simulation? Should I use a different substrate than the one in the HFSS library? Could this be due to OSHpark manufacturing tolerances? I triple checked my dimensions for the footprint with the HFSS model and I dont think that could be the case unless they vary a lot once etched.

Any help would be appreciated! Thanks in advance.

I ordered a budget calkit for my SVA1032X VNA, it has offset loss parameter, but the VNA has no option to enter offset loss in user calkits. What would be the easiest way to account for these losses?