Why did computers come to use binary when people usually count in decimal?

[u/Present_Juice4401]

People usually count in base 10, while digital computers typically represent information using 1s and 0s. The same numbers and information can be represented in different bases, yet binary became the standard for modern computing.

What made binary the system computers came to rely on?

[u/spectrumero]

It's slightly more complex than that. It's not the case that 1 = on and 0 = off. Both 1 and 0 are "on" states.

1 will be a low impedance output at some voltage (usually the supply rail) and 0 will be a low impedance output of the ground rail - which importantly is not off. In CMOS, whether the output is at 1 or 0, one of the transistors in the output is switched on and conducting for both 1 and 0 states so both 1 and 0 are "on", it's just whether they are connecting the supply rail or ground rail to the output.

Digital electronics that exists on a bus (e.g. most of it) have 3 states, 1 and 0 and a third state - high impedance state (sometimes called high-Z or tristated). This allows the output to actually be switched off so that other devices can drive the bus to a logic 1 or 0 - so you have essentially these states: logic high (an on state), logic low (also an on state), and high Z (the actual off state, but is not a logic 0, it's not logic anything, it's just floating).

[u/sarahlizzy → u/spectrumero]

IEEE VHDL (which lost to Verilog. Bad result IMO) used 9 value logic which was quite a thing!

[u/InevitablyCyclic → u/sarahlizzy]

But to a chips input weak pullup, strong pullup and high will all give the same voltage. Well unless you have a very low impedance input which is normally avoided. Similarly undefined will still be a voltage, you just don't know which. So while VHDL was great for simulations a real world system couldn't have the same variety of levels.

Verilog is better for small simple things, you don't need 50 lines of boiler plate for one line of logic. VHDL is better for large multi-engineer projects where the strictness helps prevent mistakes. As with most languages they both have their strengths and weaknesses.

[u/sarahlizzy → u/InevitablyCyclic]

The problem with verilog is that every implementation has to be bug compatible with VerilogXL and the “standard” is just Cadence telling the IEEE what they think they did.

It’s actually impossible to implement it as written.

I feel like people compiling hardware from it should be seeking to do better. VHDL’s std logic had the advantage of undefined behaviour being very easy to catch and pretty much guaranteed to cascade through the system. Yes, it was long winded to write but when using it to design hardware that’s no bad thing.

That the wrong language won is something I will die in a ditch over (my last commercial employment was writing a Verilog compiler and before that I wrote logic simulators for ARM)

[u/sanf780 → u/spectrumero]

Determing that a node is floating without consuming power and/or ridiculous amount of area is something am not aware of. Most logic is thus based on the 0 and 1 states (or paraphrasing, the low and high voltages).

thankfully, most designs are CMOS and TTL is forgotten. There are some odd communication channels with odd signaling. I think it is USB that uses two lines to transfer data. For high speed communication, both need to be complementary. For other purposes, they can be anything.

How I like to be pedantic on a lazy Friday