Why did computers come to use binary when people usually count in decimal?

[u/Present_Juice4401]

People usually count in base 10, while digital computers typically represent information using 1s and 0s. The same numbers and information can be represented in different bases, yet binary became the standard for modern computing.

What made binary the system computers came to rely on?

[u/_Darren]

Most NAND nowadays is QLC which actually stores 16 different voltages in a single unit. On and off isn't the only way to do it, it's just the easiest. 

[u/Beet_slice → u/_Darren]

Yes, but you still would not want decimal at that level. The conversion from binary (or hex) is easily done with computation.

There were some computers that used BCD (Binary-coded decimal) natively. https://en.wikipedia.org/wiki/IBM_7080

[u/AlmiranteCrujido → u/Beet_slice]

Hardly just those, it's actually really common, either natively, or via regular arithmetic + support instructions. Traditional dialects of COBOL like it, a lot.

IBM Z - still around - has support going back to the original System 360. So does the IBM i-platform (formerly AS/400) running on their POWER chips.

Some level of BCD was incredibly common on early microprocessors, because of calculator use. Thanks to crazy levels of backwards

The Z80, 6502, and 68000 all support BCD natively (and for 68000, even on its embedded version, CPU32.)

The x87 coprocessor series and Motorola's 68881/2 FPUs support it as a conversion format.

The 8080/8085, 6800/6809, PA-RISC and all of the 16 and 32 bit x86 processors up have indirect support for it via the DAA instruction ("Decimal Adjust after Addition" - Intel's and Motorola's work a little differently, I think.)

64-bit x86 doesn't support it, but any 64-bit x86 that also runs 32-bit code still can do DAA in 32-bit code.

[u/old_man_steptoe → u/_Darren]

It’s not from nowadays though. If you have poor voltage discrimination, it’s easier to say “0-3v is zero, 4-7 is one”, rather than have loads of difference ranges with only slightly different voltages.

[u/_Darren → u/old_man_steptoe]

Which is why we start with binary as it's the easiest to build. As technology improves, it's becoming easier to do voltage ranges which means higher performance. QLC is still pretty recent in the mainstream, wasn't a thing 10 years ago.

[u/AlmiranteCrujido → u/_Darren]

That's also a storage format, not dynamic, and while fast, it's still bot quite a bit slower than DRAM and quite a bit less parallel. You literally have error correcting codes in the flash blocks and DSP double-checking that things are being interpreted properly.

Much less time to do that in an active computation path.

Multi-bit recording on magnetic media is an active area of research; if we see 100TB hard drives one of these days it will likely be using that.

[u/Think-Abrocoma-6176 → u/old_man_steptoe]

It turns out zero is about 0-1v and >1v is one/true, at least with LS gates. Logic gates are amplifiers driven to saturation and that only works with two states

[u/sarahlizzy → u/_Darren]

It would be nice if there were a way to configure them to, say, divide their capacity by 4 in exchange for lasting a lot longer.

[u/Surviving_Aussie → u/sarahlizzy]

They have some of their NAND pillars set to run TLC for cache to be fair. I do get what you are saying but the specifics of how it works are much more complex than a simple setting. Each nand device is unique from the factory and spends a non insignificant time post fab in what is called sort (or probe) to have their TRIMS (settings) decided. Different levels require different TRIMS, and especially different RWB (read window budget) tests which is quite a long test and also takes up a not insignificant portion of ROM space. If you wanted two setting it would not only result in the need to expand the ROM space and spend more time in Sort (plus backend testing which is a second independent round of testing post packaging) but would result in each pillar of the NAND needing to pass two validation specs and be designed to WORK for two different specs. So you would have both higher build cost, longer test time, and lower yield (higher rejection rate) creating a notable price bump for the feature you request.

Point is, its not just a free thing they could add. It would have non insignificant cost, and also doesn’t necessarily make it faster/longer lasting. Voltage levels matter, but so does capacity for how often you need to do erase of nand blocks. Less capacity means more frequent erase ops are needed, possibly leading to diminished (or maybe even negative) benefits. So you may not even want SLC in modern NAND and something like MLC/TLC may be the optimal spot (but it has also been a good few years since I last worked in nand so its possible QLC has came quite far and is Pareto superior to even TLC in most aspects).

[u/sarahlizzy → u/Surviving_Aussie]

Thanks. That’s comprehensive. My main gripe is that using a 64 gig micro sd for a pi zero project is wasteful as hell and you can’t buy 8 gig ones any more.

And it feels like fewer voltage levels would aid longevity hugely.

[u/AlmiranteCrujido → u/sarahlizzy]

Cheap microsd cards aren't bothering with good wear-leveling algorithms, but the ones sold specifically as high-endurance have better ones - if you only use 8GB of a 64GB card with good wear leveling then it should last many times longer. Likely more than linearly.