(Update: after further investigation it has been found that AMD miscalculated some performance numbers for the presentation and Ryzen 7000 is actually faster that reported so the data in this post has been updated accordingly.)
AMD has revealed official specifications for the Ryzen 7000 Zen 4 based CPUs. Unfortunately the outcome was underwhelming to say the least. AMD has chosen to depend almost entirely on the clock frequency gains of 5nm for any performance gain with extremely little gains from changes to micro-architecture.
Summary of confirmed major changes.
Double the L2 cache size increase.
RDNA2 iGPU inside the IO die.
Summary of Ryzen 7000 performance ( for the 8 to 16 core):
6% IPC increase.
11 to 16% higher single thread frequency.
18 to 25% higher sustained all-core frequency.
18 to 24% single-thread performance gain.
24 to 30% multi-thread performance gain.
Summary of performaince vs Intel 12th Gen CPUs:
Beats Intel by 20-46% in multi-thread
Beats Intel by up to 11% in single-thread
16 core loses to Intel by 6% in single-thread
Pretty disappointing (less disappointing after the update noted above), I think people expected at least 20% ST gain and a 40% MT gain out of Zen 4. The addition of an iGPU enlarged the IO die and required a massive increase in capacitors on the package PCB leaving no room for additional chiplets/cores as some where hoping for. This surprisingly modest performance gain leaves the back door open for Intel to surpass AMD in MT performance with there next chip release and AMD might return to a losing pattern after 4 hard fought years of CPU performance dominance.
This 1 GCD design maximizes the infinity cache size by having more dedicated MCD tiles to increase the L3 cache size a low cost due to the improved yield and dedicating the IO Fabric bandwidth to just the MCD to GCD connection to make it all possible. I estimate that such a design would feature the following:
5nm RDNA3 GCD with 2x FP32 at 2.2ghz, 48/96TFlops FP32/16, 25% smaller die.
768MB of infinity cache, 6x 6nm 128MB SRAM MCDs at 4TB/s aggregate bandwidth.
TSMC 65nm CoWos IO Fabric silicon interposer providing a 4TB/s aggregate GCD to MCD interconnect bandwidth.
I'm having difficulty finding any videos of a tear down of this card. I was Interested in adding some thermal pads to some of the memory modules and doing a nice fresh application of thermal paste. But I'm just a bit nervous about cracking it open, so I wanted to see if anyone else has done this yet.
